Hardware-Efficient Logic Camouflaging for Monolithic 3-D ICs
Hardware-Efficient Logic Camouflaging for Monolithic 3-D ICs
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DOI：
10.1109/tcsii.2017.2749523
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发表时间：
2018-06
期刊：
影响因子：
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通讯作者：
Chen Yan;Jaya Dofe;Scott Kontak;Qiaoyan Yu;E. Salman
中科院分区：
文献类型：
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作者：
Chen Yan;Jaya Dofe;Scott Kontak;Qiaoyan Yu;E. Salman
电路伪装是一种布局级技术，可阻止基于图像分析的反向工程攻击。提出了一种有效的单层3-D集成电路（IC）的高效虚拟接触方法。 3-D IC实现了通过细粒度单层间静脉启用超高密度设备的集成。开发标准细胞库是为了评估伪装对大型2-D和整体3-D IC的影响。这些图书馆用于设计伪装的Simon（轻量级密码）和几个学术基准。仿真结果表明，整体3-D技术非常有效，可以促进伪装技术，以防止反向工程攻击。以平时特征的略有降解为代价，单片3-D技术不仅消除了该区域，而且消除了与伪装有关的电源开销。
Circuit camouflaging is a layout-level technique to thwart image analysis-based reverse engineering attacks. An efficient dummy contact-based camouflaging method for monolithic 3-D integrated circuits (ICs) is proposed. 3-D ICs achieve ultra-high density device integration enabled by fine-grained monolithic inter-tier vias. Standard cell libraries are developed to evaluate the effects of circuit camouflaging on large-scale 2-D and monolithic 3-D ICs. These libraries are used to design a camouflaged SIMON (lightweight block cipher) and several academic benchmarks. Simulation results demonstrate that the monolithic 3-D technology is highly effective to facilitate the utilization of the camouflaging technique against reverse engineering attacks. At the expense of a slight degradation in timing characteristics, monolithic 3-D technology eliminates not only the area but also the power overhead related to camouflaging.