64 ×64 GM-APD array-based readout integrated circuit for 3D imaging applications
64 ×64 GM-APD array-based readout integrated circuit for 3D imaging applications
复制标题
适用于 3D 成像应用的 64 × 64 GM-APD 基于阵列的读出集成电路
DOI：
10.1007/s11432-018-9712-7
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发表时间：
2019
期刊：
影响因子：
--
通讯作者：
Sun Weifeng
中科院分区：
文献类型：
--
作者：
Wu Jin;Qian Zhiming;Zhao Yang;Yu Xiangrong;Zheng Lixia;Sun Weifeng
利用工作在盖革模式下的雪崩光电二极管探测器的高灵敏度，采用包括两段时间-数字转换器(TDC)的阵列读出集成电路(ROIC)进行宽动态时间间隔测量，其中1位低段TDC是通过区分单相时钟周期来实现的。采用台积电0.18-μm互补金属氧化物半导体工艺制作的×GM-APD型阵列读出电路，最高工作频率为500 MHz，由外部锁相环时钟提供。时间分辨率降低到<；1 ns，最大范围为4μS；最低有效位(LSB)和积分非线性(INL)分别限制在-0.15到0.15和-0.3到0.32LSB；在20 kHz的帧速率下，功耗为490 mW。所开发的读出电路以两种不同的方式成功地用于成像应用。
Using the high sensitivity of the avalanche photodiode (APD) detector operated in the Geigermode (GM), an array readout integrated circuit (ROIC) comprising a two-segment time-to-digital converter (TDC) is employed for wide-dynamic time interval measurement, where a 1-bit low-segment TDC is implemented by discriminating a single-phase clock period. The proposed 64 ×64 GM-APD array ROIC fabricated using Taiwan semiconductor manufacturing company (TSMC) 0.18-μm complementary metal oxide semiconductor (CMOS) technology can operate at a maximum frequency of 500 MHz provided by an external phase-locked loop clock. The time resolution is reduced to < 1 ns along with a maximum range of 4 μs; the differential non-linearity (DNL) and integral non-linearity (INL) are restricted to approximately-0.15 to 0.15 least significant bit (LSB) and-0.3 to 0.32 LSB, respectively; and the power consumption is 490 mW under a frame rate of 20 kHz. The developed ROIC is successfully used in imaging applications in two different ways.