Conditional pre-charge techniques for power-efficient dual-edge clocking
Conditional pre-charge techniques for power-efficient dual-edge clocking
复制标题
DOI：
10.1109/lpe.2002.146709
复制
发表时间：
2002-08
期刊：
影响因子：
--
通讯作者：
N. Nedovic;M. Aleksic;V. Oklobdzija
中科院分区：
文献类型：
--
作者：
N. Nedovic;M. Aleksic;V. Oklobdzija
提出了一种新的双边触发触发器，通过抑制不用于改变状态的节点的跃迁来节省功耗。与之前发布的双边缘触发存储元件相比，该触发器的速度提高了12%，能量延迟产品降低了10%，数据活动减少了50%。采用0.18/spl mu/m工艺，1.8V电源，时钟频率250MHz进行仿真验证。这种触发器特别适用于低功耗应用。
A new dual edge-triggered flip-flop that saves power by inhibiting transitions of the nodes that are not used to change the state is presented. The proposed flip-flop is 12% faster with 10% lower energy-delay product for 50% data activity, as compared to the previously published dual edge-triggered storage elements. This was confirmed by simulation using 0.18/spl mu/m process, 1.8V power supply, and clock frequency of 250MHz. This flip-flop is particularly suitable for low-power applications.