On reducing peak current and power during test
On reducing peak current and power during test
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关于降低测试期间的峰值电流和功率
DOI：
10.1109/isvlsi.2005.53
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
I. Pomeranz
中科院分区：
文献类型：
--
作者：
Wei Li;S. Reddy;I. Pomeranz
本文提出了一种渐进匹配填充（PMF）技术，以降低宽边延迟故障测试中快速捕获周期的峰值电流和功耗。所提出的方法在生成的初始化向量中填充未指定的值（X），使得所得到的发射向量与初始化向量的汉明距离最小。所提出的方法不需要任何硬件修改，可以用来获得任何测试集，需要两个模式测试。实验结果表明，该方法使快速捕获周期的峰值电流和功耗平均降低了40.59%，对于大型ISC AS 89电路，最高可降低54.17%。
This paper presents a progressive match filling (PMF) technique to reduce the peak current and power dissipation during the fast capture cycle in broadside delay fault testing. The proposed method fills the unspecified values (X) in the generated initialization vector such that the resulting launch vector at a minimal Hamming distance from the initialization vector. The proposed method does not require any hardware modification and can be used to obtain any test sets that require two pattern tests. Experimental results show that the proposed method reduces the peak current and power dissipation during the fast capture cycle by 40.59% on average and up to 54.17% for large ISC AS 89 circuits.