Ultra Low Power Circuit Design Using Tunnel FETs
Ultra Low Power Circuit Design Using Tunnel FETs
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使用隧道 FET 的超低功耗电路设计
DOI：
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发表时间：
2012
期刊：
影响因子：
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通讯作者：
N. Vijaykrishnan
中科院分区：
文献类型：
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作者：
Ravindhiran Mukundrajan;M. Cotter;V. Saripalli;M. J. Irwin;S. Datta;N. Vijaykrishnan
无处不在的移动计算系统的激增在设计领域创造了一个新的领域，其中能源效率是最关键的设计参数。由于最终用户期望从这些类型的系统中获得更多功能，因此迫切需要评估能够克服 CMOS 限制的新兴技术。这项工作评估了一种潜在的 MOSFET 替代器件——隧道 FET (TFET) 的潜力。新颖的电路设计旨在克服 TFET 带来的独特设计挑战。对所提出的设计技术的影响进行了表征，并提出了采用所提出的设计的稀疏前缀树加法器。由于电路和技术共同探索的综合影响，观察到延迟的显着改善和能量的显着降低。
The proliferation of ubiquitous and mobile computing systems has created a new segment in the design space where energy efficiency is the most critical design parameter. With the end user expecting more functionality from these types of systems, there is a pressing need to evaluate emerging technologies that can overcome the limitations of CMOS. This work evaluates the potential of one such prospective MOSFET replacement device - the Tunnel FET (TFET). Novel circuit designs are presented to overcome unique design challenges posed by TFETs. The impacts of the proposed design techniques are characterized and a sparse prefix tree adder employing the proposed designs is presented. A considerable improvement in delay and significant reduction in energy is observed due to the combined impact of circuit and technology co-exploration.