Multiple Si layer ICs: motivation, performance analysis, and design implications
Multiple Si layer ICs: motivation, performance analysis, and design implications
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DOI：
10.1145/337292.337394
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发表时间：
2000-06
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影响因子：
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通讯作者：
S. Souri;K. Banerjee;A. Mehrotra;K. Saraswat
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文献类型：
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作者：
S. Souri;K. Banerjee;A. Mehrotra;K. Saraswat
超大规模集成电路的不断缩小正在减少门延迟，但迅速增加互连延迟。半导体工业协会（SIA）的路线图预测，超过130纳米技术节点，先进的超大规模集成电路的性能改善可能会开始饱和，除非从目前的集成电路架构的范式转变被引入。本文提出了一个全面的分析处理集成电路与多层硅层（3-D集成电路）。它示出了显着的性能改善（超过145%）和减少线限制的芯片面积可以实现与3-D集成电路与垂直层间互连（VILIC）。这种分析基于将芯片划分为单独的块，每个块占据单独的物理层。提出了一种优化不同互连层之间互连分布的方案，并量化了将中继器转移到上硅层的效果。此外，还对双层硅集成电路进行了热分析。它表明，使用热负责任的设计和/或高性能散热技术，芯片温度与两个硅层的IC可以降低远低于目前的芯片温度。最后，还讨论了3-D结构对几种电路设计的影响。
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the 130 nm technology node, performance improvement of advanced VLSI is likely to begin to saturate unless a paradigm shift from present IC architecture is introduced. This paper presents a comprehensive analytical treatment of ICs with multiple Si layers (3-D ICs). It is shown that significant improvement in performance (more than 145%) and reduction in wire-limited chip area can be achieved with 3-D ICs with vertical inter-layer interconnects (VILICs). This analysis is based on dividing a chip into separate blocks, each occupying a separate physical level. A scheme to optimize interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis. Furthermore, thermal analysis of ICs with two Si layers is presented. It is demonstrated that using a thermally responsible design and/or a high-performance heat sinking technology, die temperatures for ICs with two Si layers can be reduced well below present die temperatures. Finally, implications of 3-D architecture on several circuit designs are also discussed.