Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications
Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications
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DOI：
10.1109/jssc.2009.2022219
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发表时间：
2009-07
影响因子：
5.4
通讯作者：
H. Kondo;S. Otani;M. Nakajima;O. Yamamoto;N. Masui;N. Okumura;M. Sakugawa;M. Kitao;K. Ishimi;Masayuki Sato;Fumitaka Fukuzawa;Satoshi Imasu-;N. Kinoshita;Y. Ota;K. Arimoto;Toru Shimizu
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文献类型：
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作者：
H. Kondo;S. Otani;M. Nakajima;O. Yamamoto;N. Masui;N. Okumura;M. Sakugawa;M. Kitao;K. Ishimi;Masayuki Sato;Fumitaka Fukuzawa;Satoshi Imasu-;N. Kinoshita;Y. Ota;K. Arimoto;Toru Shimizu
异构多核片上系统（SoC）已经被开发用于需要安全DRM（数字版权管理）的高清（HD）多媒体应用。SoC集成了三种类型的处理器：两个用于密码和高分辨率视频解码的专用加速器;一个通用加速器（MX）;和三个CPU。这就是我们的SoC如何通过为处理大量数据的视频处理应用定制的硬件实现高性能和低功耗。为了实现安全的数据控制，采用了硬件内存管理和软件系统虚拟化。系统的安全性是系统硬件和软件协同工作的结果。此外，我们的SiP（系统级封装）通过DDR2 SDRAM和闪存提供了高度防篡改的系统，这些内存在一个封装中包含机密信息。这款安全多媒体处理器提供了一种解决方案，可在处理涉及数字内容交付的计费事务时保护内容并安全地交付安全敏感信息。该SoC采用90 nm通用CMOS工艺实现。
A heterogeneous multicore system-on-chip (SoC) has been developed for high-definition (HD) multimedia applications that require secure DRM (digital rights management). The SoC integrates three types of processors: two specific-purpose accelerators for cipher and high-resolution video decoding; one general-purpose accelerator (MX); and three CPUs. This is how our SoC achieves high performance and low power consumption with hardware customized for video processing applications that process a large amount of data. To achieve secure data control, hardware memory management and software system virtualization are adopted. The security of the system is the result of the cooperation between the hardware and software on the system. Furthermore, a highly tamper-resistant system is provided on our SiP (System in a package), through DDR2 SDRAMs and a flash memory that contain confidential information in one package. This secure multimedia processor provides a solution to protect contents and to safely deliver secure sensitive information when processing billing transactions that involve digital content delivery. The SoC was implemented in a 90 nm generic CMOS technology.