On automating delayered IC analysis for hardware IP protection
On automating delayered IC analysis for hardware IP protection
复制标题
硬件 IP 保护的自动化延迟 IC 分析
DOI：
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
Michail Maniatakos
中科院分区：
文献类型：
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作者：
Esha Sarkar;Michail Maniatakos
集成电路（IC）的制造外包给第三方代工厂，以缩短上市时间和降低生产成本。外包使IC容易受到恶意修改。这些被称为硬件特洛伊木马（HT）的恶意电路修改会篡改知识产权核心的完整性，因此必须准确检测。检测HT的一种高度准确的方法是通过对逆向工程芯片进行耗时的物理检查。显然，对所有可疑芯片进行物理检查是不现实的。因此，从逆向工程一个受感染的IC获得的知识应被用来检测木马非侵入性的其他IC。在其他可疑芯片中的额外恶意逻辑可以使用导致其检测的合适测试模式来触发。然而，为了便于使用测试模式进行检测，应该将HT映射到黄金电路，并且应该使用自动化工具来找到适当的模式。在这项工作中，我们通过讨论所需的步骤和确定每个步骤中未解决的挑战来探索这种两步HT检测方法的可行性。
Fabrication of Integrated Circuits (ICs) is outsourced to third-party foundries to decrease time to market and production cost. Outsourcing renders the ICs vulnerable to malicious modifications. These malicious circuit modifications, known as Hardware Trojans (HTs), tamper with the integrity of intellectual property cores and hence, must be detected accurately. A highly accurate method for detecting HTs is through time-consuming physical inspection of reverse-engineered chips. Apparently, physically inspection of all suspected chips is unrealistic. Therefore, the knowledge gained from reverse engineering a single infected IC should be used to detect trojans non-invasively in other ICs. The extra malicious logic, in other suspected chips, can be triggered using suitable test patterns leading to its detection. In order to facilitate detection using test patterns, however, the HT should be mapped to the golden circuit, and automated tools should be used to find appropriate patterns. In this work, we explore the feasibility of this two-step methodology for HT detection by discussing the required steps and identifying the unsolved challenges in each step.