Enhancing workload-dependent voltage scaling for energy-efficient ultra-low-power embedded systems
Enhancing workload-dependent voltage scaling for energy-efficient ultra-low-power embedded systems
复制标题
增强节能超低功耗嵌入式系统的工作负载相关电压调节
DOI：
10.1145/3195970.3196046
复制
发表时间：
2018
期刊：
影响因子：
--
通讯作者：
Sartori, John
中科院分区：
文献类型：
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作者：
Mohan, Veni;Iyer, Akhilesh;Sartori, John
超低功耗（ULP）芯片组的需求比以往任何时候都要高，因为ULP嵌入式系统的激增，以支持物联网（IoT）、可穿戴设备和传感器网络等不断增长的应用。由于ULP系统也受到成本限制，因此它们倾向于采用通用处理器（GPP）而不是更节能的ASIC，即使它们通常在系统的生命周期内运行单个应用程序。先前的工作表明，可以在不降低频率的情况下降低操作电压，从而降低这种系统的功率，因为系统的固定软件栈通常仅执行处理器路径的子集，并且未执行的路径不需要满足系统正确工作的时序约束。在这种情况下，我们找到了额外的范围，通过智能优化处理器设计的基础上，系统的应用程序特定的活动特性，以允许更低的安全工作电压的功耗降低。我们演示了自动化技术，可最大限度地降低系统的特定应用电压，与优化前的特定应用最小电压相比，平均可额外节省35%的功耗，与标称电压下的原始设计相比，可节省48%的总功耗。
Ultra-low-power (ULP) chipsets are in higher demand than ever due to the proliferation of ULP embedded systems to support growing applications like the Internet of Things (IoT), wearables and sensor networks. Since ULP systems are also cost constrained, they tend to employ general purpose processors (GPPs) rather than more energy-efficient ASICs, even though they typically run a single application for the lifetime of the system. Prior work showed that it is possible to reduce the operating voltage and thus the power of such systems without reducing the frequency, since the fixed software stack of a system typically only exercises a subset of a processor's paths, and unexercised paths need not meet timing constraints for the system to work correctly. In this context, we find additional scope for power reduction by intelligently optimizing the processor design based on the system's application-specific activity characteristics to allow an even lower safe operating voltage. We demonstrate automated techniques that maximize the application-specific voltage reduction for a system, resulting in 35% additional power savings, on average, compared to the application-specific minimum voltage before optimization and 48% total power savings compared to the original design at nominal voltage.