2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS-猫眼课题宝

DOI：

10.1109/jssc.2014.2349974

发表时间：

2014-09

期刊：

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)

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通讯作者：

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其他

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作者：

H. Kimura;P. Aziz;Tai Jing;A. Sinha;R. Narayan;Hairong Gao;Ping Jing;Gary Hom;Anshi Liang;E. Zhang;A. Kadkol;R. Kothari;G. Chan;Yehui Sun;Benjamin Ge;Jason Zeng;K. Ling;Michael C. Wang;A. Malipatil;S. Kotagiri;Lijun Li;C. Abel;Freeman Y. Zhong

高速SerDes必须满足高速运行、密集均衡技术、低功耗、小面积和鲁棒性等多重挑战。为了满足OIF CEI-25G-LR、CEI-28G-MR/SR/VSR、IEEE802.3bj和32G-FC等新标准，数据速率提高到25至28Gb/s，比上一代SerDes提高75%以上。对于在单芯片中集成数百个通道的 SerDes 应用，在保持高性能的同时，功耗是非常重要的因素。之前有一些 28Gb/s 或更高数据速率的作品 [1-2]。他们使用展开的 DFE 来满足关键时序裕度，但展开的 DFE 结构增加了 DFE 切片器的数量，从而增加了整体功耗和芯片面积。为了应对这些挑战，我们引入了几种电路和架构技术。模拟前端 (AFE) 在跨阻放大器 (TIA) 中采用单级架构和紧凑型片上无源电感器，可提供 15dB 的升压。升压是自适应的，并且其自适应环路通过使用群延迟自适应（GDA）算法与判决反馈均衡器（DFE）自适应环路解耦。 DFE 具有半速率 1-tap 展开结构，带有 2 个总误差锁存器，可降低功耗和面积。基于两级传感放大器的限幅器实现了 15mV 的灵敏度和 DFE 时序收敛。我们还开发了一种使用新型有源电感器电路的高速时钟缓冲器。该有源电感器电路能够控制输出共模电压以优化电路工作点。

A high-speed SerDes must meet multiple challenges including high-speed operation, intensive equalization technique, low power consumption, small area and robustness. In order to meet new standards, such a OIF CEI-25G-LR, CEI-28G-MR/SR/VSR, IEEE802.3bj and 32G-FC, data-rates are increased to 25 to 28Gb/s, which is more than 75% higher than the previous generation of SerDes. For SerDes applications with several hundreds of lanes integrated in single chip, power consumption is very important factor while maintaining high performance. There are several previous works at 28Gb/s or higher data-rate [1-2]. They use an unrolled DFE to meet the critical timing margin, but the unrolled DFE structure increases the number of DFE slicers, increasing the overall power and die area. In order to tackle these challenges, we introduce several circuits and architectural techniques. The analog front-end (AFE) uses a single-stage architecture and a compact on-chip passive inductor in the transimpedance amplifier (TIA), providing 15dB boost. The boost is adaptive and its adaptation loop is decoupled from the decision-feedback equalizer (DFE) adaptation loop by the use of a group-delay adaptation (GDA) algorithm. DFE has a half-rate 1-tap unrolled structure with 2 total error latches for power and area reduction. A two-stage sense-amplifier-based slicer achieves a sensitivity of 15mV and DFE timing closure. We also develop a high-speed clock buffer that uses a new active-inductor circuit. This active-inductor circuit has the capability to control output-common-mode voltage to optimize circuit operating points.

2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS

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