Minimizing Peak Power Consumption during Scan Testing: Structural Technique for Don't Care Bits Assignment
Minimizing Peak Power Consumption during Scan Testing: Structural Technique for Don't Care Bits Assignment
复制标题
最小化扫描测试期间的峰值功耗：无关位分配的结构技术
DOI：
10.1109/rme.2006.1689897
复制
发表时间：
2006
期刊：
影响因子：
--
通讯作者：
H. Wunderlich
中科院分区：
文献类型：
--
作者：
N. Badereddine;P. Girard;S. Pravossoudovitch;C. Landrault;A. Virazel;H. Wunderlich
扫描结构虽然广泛应用于现代测试设计中，但功耗昂贵。在本文中，我们首先讨论的问题，过度的峰值功耗在扫描测试。接下来，我们将展示在测试周期（即发射和捕获之间）期间注意高电流水平是高度相关的，以避免噪声现象，如IR压降或接地反弹。然后，我们提出了一个解决方案的基础上，在确定性的测试模式，考虑被测电路的结构信息的无关位的功耗感知分配。在ISCAS'89和ITC'99基准电路上进行了实验。这些结果表明，所提出的技术提供了峰值功率降低和测试序列长度增加之间的最佳折衷
Scan architectures, though widely used in modern designs for testing purpose, are expensive in power consumption. In this paper, we first discuss the issues of excessive peak power consumption during scan testing. We next show that taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant so as to avoid noise phenomena such as IR-drop or ground bounce. Then, we propose a solution based on power-aware assignment of don't care bits in deterministic test patterns that considers structural information of the circuit under test. Experiments have been performed on ISCAS'89 and ITC'99 benchmark circuits. These results show that the proposed technique provides the best tradeoff between peak power reduction and increase of test sequence length