Optimal Zero-Aliasing Space Compaction of Test Responses
Optimal Zero-Aliasing Space Compaction of Test Responses
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测试响应的最佳零混叠空间压缩
DOI：
10.1109/12.736427
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发表时间：
1998
期刊：
影响因子：
--
通讯作者：
J. Hayes
中科院分区：
文献类型：
--
作者：
K. Chakrabarty;B. Murray;J. Hayes
许多内置的自测试（BIST）方案将k-输出电路的测试响应压缩为q个签名流，其中q/spl为Lt/k，这个过程称为空间压缩。这种压实方法的有效性可以通过其压实比c=k/q来衡量。高压缩比可能会引入混叠，当错误的测试响应映射到无错误的签名时就会发生混叠。研究了最大压缩比为c/sub max/的零混叠空间压缩电路的设计问题。我们引入测试响应的图表示来研究空间压实过程，并将空间压实机的设计与图着色问题联系起来。给定待测电路、故障模型和测试集，我们确定q/sub min/，得到c/sub max/=k/q/sub min/。这为基于签名的BIST的成本提供了一个基本的界限。我们发现q/sub / min//spl对所有ISCAS 85基准电路来说都是/2。我们开发了一个系统的设计程序来合成空间压缩电路，并将其应用于一些ISCAS 85电路。最后，我们描述了多步压缩，它允许在任意q下实现零混叠，即使q/sub min/>为1。
Many built-in self-testing (BIST) schemes compress the test responses from a k-output circuit to q signature streams, where q/spl Lt/k, a process termed space compaction. The effectiveness of such a compaction method can be measured by its compaction ratio c=k/q. A high compaction ratio can introduce aliasing, which occurs when a faulty test response maps to the fault-free signature. We investigate the problem of designing zero-aliasing space compaction circuits with maximum compaction ratio c/sub max/. We introduce a graph representation of test responses to study the space compaction process and relate space compactor design to a graph coloring problem. Given a circuit under test, a fault model, and a test set, we determine q/sub min/, which yields c/sub max/=k/q/sub min/. This provides a fundamental bound on the cost of signature-based BIST. We show that q/sub min//spl les/2 for all the ISCAS 85 benchmark circuits. We develop a systematic design procedure for the synthesis of space compaction circuits and apply it to a number of ISCAS 85 circuits. Finally, we describe multistep compaction, which allows zero aliasing to be achieved with any q, even when q/sub min/>1.