A Quantitative Defense Framework against Power Attacks on Multi-tenant FPGA
A Quantitative Defense Framework against Power Attacks on Multi-tenant FPGA
复制标题
多租户 FPGA 的强力攻击定量防御框架
DOI：
10.1145/3400302.3415694
复制
发表时间：
2020
期刊：
影响因子：
--
通讯作者：
Xiaolin Xu
中科院分区：
文献类型：
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作者：
Yukui Luo;Xiaolin Xu
各种机器学习算法的发展和应用对计算能力提出了更高的要求。因此，现场可编程门阵列(FGA)被用作硬件加速器，最近由领先供应商部署在云服务器中，以提供可重新配置的计算能力。虽然这样的云-FPGA平台带来了显著的性能优势，但它也创建了一个独特的攻击面，其中一个FPGA的硬件资源被多个用户共享。针对配电网的电力攻击是对多租户现场可编程门阵列最具威胁性的攻击之一。在这种攻击中，恶意用户利用功率掠夺电路来操纵PDN并导致电压下降，从而向受害者应用程序注入时序错误。此外，由于大多数云FPGA用于计算密集型任务，消耗大量功率，因此，典型的FPGA应用即使在没有电源攻击的情况下，也可能会遇到时序故障。与电源攻击不同，我们将此问题归类为可靠性问题。为了全面缓解非恶意或恶意电压降带来的可靠性和安全性问题，本文引入了一种量化防御框架。该框架提供了静态调频和动态调频两种防御方式来管理现场可编程门阵列应用的时钟频率。频率调整策略基于量化对抗性电路和可以注入的电压降之间的关系。该框架提供了一个延迟频率对表，可以预先配置该表来控制FPGA应用程序的运行时时钟频率。为了实用，该框架利用了现有的片上时钟管理组件，如混合模式时钟管理器(MMCM)和锁相环(PLL)。此外，为了辅助频率调节，我们提出了一种能够准确量化实时压降的片上传感器。在Xilinx NetFPGA上通过开源基准测试和实际的高级加密标准(AES)实现，验证了该框架的性能。实验结果表明，该方法能有效地降低电压降引起的安全性和可靠性问题。为了全面缓解非恶意或恶意电压降带来的可靠性和安全性问题，本文引入了一种量化防御框架。该框架提供了静态调频和动态调频两种防御方式来管理现场可编程门阵列应用的时钟频率。频率调整策略基于量化对抗性电路和可以注入的电压降之间的关系。该框架提供了一个延迟频率对表，可以预先配置该表来控制FPGA应用程序的运行时时钟频率。为了实用，该框架利用了现有的片上时钟管理组件，如混合模式时钟管理器(MMCM)和锁相环(PLL)。此外，为了辅助频率调节，我们提出了一种能够准确量化实时压降的片上传感器。在Xilinx NetFPGA上通过开源基准测试和实际的高级加密标准(AES)实现，验证了该框架的性能。实验结果表明，该方法能有效地降低电压降引起的安全性和可靠性问题。
The development and application of various Machine Learning algorithms demand high computing capabilities. As a result, field-programmable gate arrays (FPGAs) are being used as hardware accelerators, and more recently deployed in cloud servers by leading vendors to provide reconfigurable computing capabilities. Although such cloud-FPGA platform is bringing significant performance benefits, it also creates a unique attack surface where the hardware resources of an FPGA are shared by multiple users. Power attack targeting the power distribution network (PDN) is among the most threatening ones against multi-tenant FPGAs. In such attack, the malicious users leverage power plundering circuits to manipulate the PDN and cause a voltage drop, thus injecting timing faults to the victim applications. Besides, since most cloud-FPGAs are being used for computing-intensive tasks that consume a large amount of power, therefore, typical FPGA applications may still encounter timing faults even without power attacks. Unlike power attacks, we classify this problem as a reliability issue. To comprehensively mitigate the reliability and security issues caused by a non-malicious or malicious voltage drop, in this paper, we introduce a quantitative defense framework. The proposed framework provides a two-fold defense method: static and dynamic frequency scaling, to manage the clock frequency of the FPGA applications. The frequency scaling strategy is based on quantifying the relationship between the adversarial circuit and the voltage drop that can be injected. The proposed framework provides a delay-frequency pair table, which can be pre-configured to control the run-time clock frequency of the FPGA application. For practical applicability, the proposed framework utilizes the existing on-chip clock management components like mixed-model clock manager (MMCM) and phase-locked loop (PLL). Additionally, to assist the frequency scaling, we propose an on-chip sensor that can accurately quantify the real-time voltage drop. The performance of the proposed framework is validated with open-source benchmarks and real-world Advanced Encryption Standard (AES) implementation on an Xilinx NetFPGA. The experimental results demonstrate the effectiveness of the proposed method in mitigating security and reliability issues caused by a voltage drop. To comprehensively mitigate the reliability and security issues caused by a non-malicious or malicious voltage drop, in this paper, we introduce a quantitative defense framework. The proposed framework provides a two-fold defense method: static and dynamic frequency scaling, to manage the clock frequency of the FPGA applications. The frequency scaling strategy is based on quantifying the relationship between the adversarial circuit and the voltage drop that can be injected. The proposed framework provides a delay-frequency pair table, which can be pre-configured to control the run-time clock frequency of the FPGA application. For practical applicability, the proposed framework utilizes the existing on-chip clock management components like mixed-model clock manager (MMCM) and phase-locked loop (PLL). Additionally, to assist the frequency scaling, we propose an on-chip sensor that can accurately quantify the real-time voltage drop. The performance of the proposed framework is validated with open-source benchmarks and real-world Advanced Encryption Standard (AES) implementation on an Xilinx NetFPGA. The experimental results demonstrate the effectiveness of the proposed method in mitigating security and reliability issues caused by a voltage drop.