A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller
A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller
复制标题
具有异步反馈 CTLE 和适用于内存控制器的自适应 3 步眼图检测算法的 4266 Mb/s/引脚 LPDDR4 接口
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发表时间：
2018
期刊：
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通讯作者：
Suhwan Kim
中科院分区：
文献类型：
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作者：
Mino Kim;Joo;Sungphil Choi;Gi;H. Ko;D. Jeong;Suhwan Kim
提出了一种用于存储控制器的4266 Mb/s/pin LPDDR 4接口电路，该电路采用异步反馈连续时间线性均衡器（AF-CTLE）和自适应三步眼检测算法。AF-CTLE通过施加大于噪声的偏移来消除DQS的毛刺而无需训练，并且通过在DQ路径中作为判决反馈均衡器来操作来提高读取裕度。与2-D全扫描相比，自适应3步眼睛检测算法减少了初始化序列和重新训练中的功耗和熄灭时间。原型芯片采用65 nm CMOS工艺，采用细间距球栅阵列封装，并使用商品LPDDR4存储器进行测试。写入裕度为0.36 UI和148 mV;读取裕度从无AF-CTLE的0.30 UI和76 mV提高到有AF-CTLE的0.47 UI和80 mV。在突发写入和读取期间的功率效率分别为5.68 pJ/位和1.83 pJ/位。
A 4266Mb/s/pin LPDDR4 interface with an asynchronous feedback continuous-time linear equalizer (AF-CTLE) and an adaptive 3-step eye detection algorithm for memory controller is presented. The AF-CTLE removes the glitch of DQS without training by applying an offset larger than the noise, and improves read margin by operating as a decision feedback equalizer in DQ path. The adaptive 3-step eye detection algorithm reduces power consumption and black-out time in initialization sequence and retraining in comparison to the 2-D full scanning. A prototype chip was implemented in a 65-nm CMOS process with fine-pitch ball grid array package and tested with commodity LPDDR4 memory. The write margin was 0.36 UI and 148 mV; and the read margin was enhanced from 0.30 UI and 76 mV without AF-CTLE to 0.47 UI and 80 mV to with AF-CTLE. The power efficiency during burst write and read were 5.68 pJ/bit and 1.83 pJ/bit, respectively.