Next-Generation Design and Technology Co-optimization (DTCO) of System on Integrated Chip (SoIC) for Mobile and HPC Applications
Next-Generation Design and Technology Co-optimization (DTCO) of System on Integrated Chip (SoIC) for Mobile and HPC Applications
复制标题
适用于移动和 HPC 应用的集成芯片系统 (SoIC) 的下一代设计和技术协同优化 (DTCO)
DOI：
10.1109/iedm13553.2020.9372005
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
Douglas C. H. Yu
中科院分区：
文献类型：
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作者：
Y.K. Cheng;F. Lee;M.F. Chen;J. Yuan;Tze;K.;C. Wang;C.;C. Tsai;Douglas C. H. Yu
介绍了面向移动和高性能计算机应用的片上系统(SOIC)的新一代设计和技术协同优化(DTCO)，提出了将具有不同功能和技术的多个芯片集成到单个SoC芯片中的SOIC技术。新的DTCO包括整体芯片划分、芯片集成和互连。这些方法可用于改进上市时间和性能与成本之间的权衡。文中展示了两种堆叠式CPU和内存芯片的原型，性能提高了15%，平均点对点距离减少了30%。
This paper demonstrates the next-generation design and technology co-optimization (DTCO) of system on integrated chip (SoIC) for mobile and HPC applications, where the SoIC technology was proposed to integrate multichips with different functionality and technology into a single SoC chip. The new DTCO includes overall die partitioning, die integration, and interconnect. These methodologies can be used for improving time-to-market and trade-off between performance and cost. In this paper, two prototypes of stacking CPU and memory dies are demonstrated with 15% performance gain and 30% average point-to-point distance reduction.