Design Method of Single Flux Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates
Design Method of Single Flux Quantum Logic Circuits Using Dynamically Reconfigurable Logic Gates
复制标题
采用动态可重构逻辑门的单通量量子逻辑电路设计方法
DOI：
10.1109/tasc.2014.2387251
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发表时间：
2015
期刊：
影响因子：
--
通讯作者：
and N. Yoshikawa
中科院分区：
文献类型：
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作者：
S. Nishimoto;Y. Yamanashi;and N. Yoshikawa
在这项研究中，我们设计并测试了动态可重构与/或和与非/或非单通量量子（SFQ）逻辑门。在低频下测得的直流偏置裕度分别为99%-126%和121%-144%的AND/OR和NAND/NOR门。实验证实的AND/OR和NAND/NOR门的最大工作频率分别为36和24 GHz。我们研究了一种电路设计方法，使SFQ逻辑电路的有效设计，通过使用动态可重构SFQ逻辑门。利用布尔函数的输入数据模式依赖性，通过对动态可重构SFQ逻辑门的重新配置，设计了具有少量门的逻辑电路。作为一个案例研究，我们设计和测试的位串行SFQ全加器使用所研究的电路设计方法。与传统的位串行SFQ全加器相比，所提出的全加器的延迟减少了27%，假设时钟频率为20 GHz。我们通过低速测试确认了加法器的正确操作。
In this study, we designed and tested dynamically reconfigurable AND/OR and NAND/NOR single flux quantum (SFQ) logic gates. The measured dc bias margins at low frequency were 99%-126% and 121%-144% for AND/OR and NAND/NOR gates, respectively. The experimentally confirmed maximum operating frequencies of the AND/OR and NAND/NOR gates were 36 and 24 GHz, respectively. We investigated a circuit design method that enables the efficient design of SFQ logic circuits by using dynamically reconfigurable SFQ logic gates. The logic circuits were designed with a small number of gates using the input data pattern dependence of the Boolean function and reconfiguring the dynamically reconfigurable SFQ logic gates. As a case study, we designed and tested a bit-serial SFQ full adder using the investigated circuit design method. Compared with the conventional bit-serial SFQ full adder, the delay of the proposed full adder was reduced by 27%, assuming a clock frequency of 20 GHz. We confirmed correct operation of the adder with a low-speed test.