Graph Neural Network based Hardware Trojan Detection at Intermediate Representative for SoC Platforms
Graph Neural Network based Hardware Trojan Detection at Intermediate Representative for SoC Platforms
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DOI：
10.1145/3526241.3530827
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发表时间：
2022-06
期刊：
影响因子：
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通讯作者：
Weimin Fu;H. Yu;Orlando Arias;Kaichen Yang;Yier Jin;Tuba Yavuz;Xiaolong Guo
中科院分区：
文献类型：
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作者：
Weimin Fu;H. Yu;Orlando Arias;Kaichen Yang;Yier Jin;Tuba Yavuz;Xiaolong Guo
物联网（IoT）行业的快速增长增加了对知识产权（IP）内核的需求。越来越多的第三方供应商提出了片上系统（SoC）设计人员的安全问题。随着SoC设计的日益复杂，SoC设计人员手动诊断安全漏洞的工作量越来越大。几乎所有现有的SoC平台都使用SystemVerilog开发。然而，目前还缺乏可靠的安全静态分析工具直接处理SystemVerilog程序。由于其开源性、灵活性和可扩展性，RISC-V CPU已成为可穿戴设备、娱乐、智能恒温器等物联网应用的理想平台。提出了一种基于图神经网络的木马检测框架，用于保护SystemVerilog编写的RISC-V SoC平台免受恶意逻辑入侵。该研究正在建设中，并计划在实验部分的Ariane RISC-V CPU上进行验证。
The rapid growth of the Internet of Things (IoT) industry has increased the demand for intellectual property (IP) cores. Increasing numbers of third-party vendors have raised security concerns for System-on-Chip (SoC) designers. With the growing complexity of SoC design, the workload is overwhelming for SoC designers to diagnose security vulnerabilities manually. Almost all existing SoC platforms are developed using SystemVerilog. However, there is a lack of reliable security static analysis tools for directly processing the SystemVerilog program. Due to its open-source, flexibility and extendability, RISC-V CPU has become an ideal platform for the IoT applications such as wearable devices, entertainment, smart thermostats, etc. As a result, assuring the trustworthiness of a given RISC-V system is highly desired. This paper proposes a graph neural network-based Trojan detection framework to protect the RISC-V SoC platform written in SystemVerilog from intruding malicious logic. The study is under-construction and planned to be validated on the Ariane RISC-V CPU with several peripheral IPs in the experimental section.