Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors
Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors
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DOI：
10.1145/2228360.2228521
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发表时间：
2012-06
期刊：
影响因子：
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通讯作者：
Lei Jiang;Bo Zhao;Youtao Zhang;Jun Yang
中科院分区：
文献类型：
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作者：
Lei Jiang;Bo Zhao;Youtao Zhang;Jun Yang
多层单元自旋转移力矩磁随机存取存储器（MLC STT - MRAM）是一种新兴的非易失性存储技术，已成为构建高端嵌入式处理器二级缓存的有潜力的候选技术。然而，较长的写入延迟限制了基于MLC STT - MRAM的二级缓存的有效性。在本文中，我们通过两种新颖的设计来解决这一限制：行配对（LP）和行交换（LS）。LP通过重新组织写入速度更快的MLC软位来形成快速缓存行。LS将频繁写入的数据动态存储到这些快速缓存行中。我们的实验结果表明，LP和LS使系统性能提高了15%，能耗降低了21%。
MLC STT-MRAM (Multi-level Cell Spin-Transfer Torque Magnetic RAM), an emerging non-volatile memory technology, has become a promising candidate to construct L2 caches for high-end embedded processors. However, the long write latency limits the effectiveness of MLC STT-MRAM based L2 caches. In this paper, we address this limitation with two novel designs: Line Pairing (LP) and Line Swapping (LS). LP forms fast cachelines by re-organizing MLC soft bits which are faster to write. LS dynamically stores frequently written data into these fast cachelines. Our experimental results show that LP and LS improve system performance by 15% and reduce energy consumption by 21%.