Analog decoders and receivers for high speed applications
Analog decoders and receivers for high speed applications
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适用于高速应用的模拟解码器和接收器
DOI：
10.1109/izsbc.2002.991743
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发表时间：
2002
期刊：
影响因子：
--
通讯作者：
A. Schaefer
中科院分区：
文献类型：
--
作者：
J. Hagenauer;M. Moerz;A. Schaefer
数据传输速度的不断提高，特别是在光通道、磁记录设备和无线链路中，使得有必要寻找能够以低功耗进行高速处理的新接收器结构。模拟、非线性和高度并行操作电路可以执行均衡、差分检测、通道解码以及在某些情况下通常分配给数字处理器和电路的源解码的任务。第一个由简单解码器组件组成的原型模拟 VLSI 芯片现已推出，并且在高达 10 Gbit/s 的速度下表现良好。
The ever increasing speed of data transmission, especially in optical channels, in magnetic recording devices and in wireless links, makes it necessary to look at new receiver structures which are capable of high speed processing at low power consumption. Analog, nonlinear and highly parallel operating circuits can perform the tasks of equalization, differential detection, channel decoding and, in some cases, of source decoding which are normally assigned to digital processors and circuits. The first prototype analog VLSI chips of simple decoder components are available and perform well at speeds up to 10 Gbit/s.