Power efficient dataflow design for a heterogeneous smart camera architecture
Power efficient dataflow design for a heterogeneous smart camera architecture
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DOI：
10.1109/dasip.2017.8122128
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发表时间：
2017-09
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影响因子：
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通讯作者：
Deepayan Bhowmik;Paulo Garcia;A. Wallace;Robert J. Stewart;G. Michaelson
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作者：
Deepayan Bhowmik;Paulo Garcia;A. Wallace;Robert J. Stewart;G. Michaelson
视觉注意力建模表征场景以分割视觉感兴趣的区域，并且越来越多地被用作许多计算机视觉应用（包括监视和安全）中的预处理步骤。智能相机架构是一项新兴技术，也是现代视觉系统中安全和安全框架的基础。在本文中，我们提出了一个基于视觉显着性的摄像机架构，针对异构的CPU+FPGA平台，提出了一个智能摄像机网络基础设施的快速设计。设计流程包括图像处理算法实现、软硬件集成和网络连接。通过充分利用Algorithlow范式的特性，我们迭代地将算法规范改进为可部署的解决方案，在每个设计阶段满足不同的要求：从算法精度到硬件-软件交互，实时执行和功耗。我们的设计实现了实时运行时间的性能和优化的异步设计的功耗仅为0.25瓦。Xilinx Zynq平台上的资源使用率仍然非常低。
Visual attention modelling characterises the scene to segment regions of visual interest and is increasingly being used as a pre-processing step in many computer vision applications including surveillance and security. Smart camera architectures are an emerging technology and a foundation of security and safety frameworks in modern vision systems. In this paper, we present a dataflow design of a visual saliency based camera architecture targeting a heterogeneous CPU+FPGA platform to propose a smart camera network infrastructure. The proposed design flow encompasses image processing algorithm implementation, hardware & software integration and network connectivity through a unified model. By leveraging the properties of the dataflow paradigm, we iteratively refine the algorithm specification into a deployable solution, addressing distinct requirements at each design stage: from algorithm accuracy to hardware-software interactions, real-time execution and power consumption. Our design achieved real-time run time performance and the power consumption of the optimised asynchronous design is reported at only 0.25 Watt. The resource usages on a Xilinx Zynq platform remains significantly low.