A VGA 30 fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation
A VGA 30 fps Affine Motion Model Estimation VLSI for Real-Time Video Segmentation
复制标题
用于实时视频分割的 VGA 30 fps 仿射运动模型估计 VLSI
DOI：
10.1587/transinf.e93.d.3284
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
Y. Matsuda
中科院分区：
文献类型：
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作者：
Yoshiki Yunbe;M. Miyama;Y. Matsuda
本文描述了一种用于实时视频分割的仿射运动估计处理器。处理器利用仿射参数估计目标区域的主要运动。该处理器基于伪 M 估计算法。在原有算法中引入图像分割方法和二值权重方法，减少了数据流量和硬件成本。提出了一种像素采样方法，可将时钟频率降低 50%。像素管线架构和帧重叠方法使吞吐量翻倍。该处理器在 FPGA 上进行了原型设计；随后对其功能和性能进行了验证。它也被实现为 ASIC。核心尺寸为5.0×5.0mm2，采用0.18μm工艺、标准电池技术。该 ASIC 可以容纳时钟频率为 120MHz 的 VGA 30fps 视频。
This paper describes an affine motion estimation processor for real-time video segmentation. The processor estimates the dominant motion of a target region with affine parameters. The processor is based on the Pseudo-M-estimator algorithm. Introduction of an image division method and a binary weight method to the original algorithm reduces data traffic and hardware costs. A pixel sampling method is proposed that reduces the clock frequency by 50%. The pixel pipeline architecture and a frame overlap method double throughput. The processor was prototyped on an FPGA; its function and performance were subsequently verified. It was also implemented as an ASIC. The core size is 5.0×5.0mm2 in 0.18µm process, standard cell technology. The ASIC can accommodate a VGA 30fps video with 120MHz clock frequency.