Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL
Energy-efficient FPGA Implementation of the k-Nearest Neighbors Algorithm Using OpenCL
复制标题
使用 OpenCL 的高能效 FPGA 实现 k 最近邻算法
DOI：
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发表时间：
2016
期刊：
影响因子：
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通讯作者：
Affaq Qamar
中科院分区：
文献类型：
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作者：
F. Muslim;Alexandros Demian;Liang Ma;L. Lavagno;Affaq Qamar
现代SOC越来越多，多核体系结构和硬件加速器的结合，以较低的现代FPGA速度加快了汇编任务的执行。传统的基于GPU的加速器。在几个高级语言中考虑了算法的相当不同的实现，并比较了它们在FPGA和GPU上的性能。与GPU相比，使用FPGA特定的OPENCL编码样式并提供适当的HLS指令的效率加速度；
Modern SoCs are getting increasingly heterogeneous with a combination of multi-core architectures and hardware accelerators to speed up the execution of computeintensive tasks at considerably lower power consumption. Modern FPGAs, due to their reasonable execution speed and comparatively lower power consumption, are strong competitors to the traditional GPU based accelerators. High-level Synthesis (HLS) simplifies FPGA programming by allowing designers to program FPGAs in several high-level languages e.g. C/C++, OpenCL and SystemC. This work focuses on using an HLS based methodology to implement a widely used classification algorithm i.e. k-nearest neighbor on an FPGA based platform directly from its OpenCL code. Multiple fairly different implementations of the algorithm are considered and their performance on FPGA and GPU is compared. It is concluded that the FPGA generally proves to be more power efficient as compared to the GPU. Furthermore, using an FPGA-specific OpenCL coding style and providing appropriate HLS directives can yield an FPGA implementation comparable to a GPU also in terms of execution time. Keywords—kNN; FPGA; High-Level Synthesis; Hardware Acceleration; low-power low-energy computation; Parallel Computing; OpenCL.