Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: A review
Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: A review
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DOI：
10.1109/tdmr.2004.824359
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发表时间：
2004-03-01
影响因子：
2
通讯作者：
Kumar, MJ
中科院分区：
文献类型：
--
作者：
Chaudhry, A;Kumar, MJ
本文研究了在绝缘体上硅 (SOI) 上制造的 MOS 器件由于不良的短沟道效应 (SCE) 而导致的性能下降，因为沟道长度按比例缩放以满足高速高性能 ULSI 应用日益增长的需求。该审查评估了最近在 SOI MOSFET 中规避 SCE 的提议，并对每项尝试的具体优点和缺点进行了简短评估。讨论了一种称为双材料栅极 (DMG) SOI MOSFET 的新器件结构，并评估了其抑制 SCE 的功效，例如漏极感应势垒降低 (DIBL)、沟道长度调制和热载流子效应，所有这些都会影响超小几何尺寸 MOSFET 的可靠性。
This paper examines the performance degradation of a MOS device fabricated on silicon-on-insulator (SOI) due to the undesirable short-channel effects (SCE) as the channel length is scaled to meet the increasing demand for high-speed high-performing ULSI applications. The review assesses recent proposals to circumvent the SCE in SOI MOSFETs and a short evaluation of strengths and weaknesses specific to each attempt is presented. A new device structure called the dual-material gate (DMG) SOI MOSFET is discussed and its efficacy in suppressing SCEs such as drain-induced barrier lowering (DIBL), channel length modulation and hot-carrier effects, all of which affect the reliability of ultra-small geometry MOSFETs, is assessed.