Designing radiation hardened CMOS microelectronic components at commercial foundries: space and terrestrial radiation environments and device and circuit techniques to mitigate radiation effects
Designing radiation hardened CMOS microelectronic components at commercial foundries: space and terrestrial radiation environments and device and circuit techniques to mitigate radiation effects
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在商业代工厂设计抗辐射 CMOS 微电子元件：空间和地面辐射环境以及减轻辐射影响的设备和电路技术
DOI：
10.1109/irws.2005.1609589
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发表时间：
2005
期刊：
影响因子：
--
通讯作者：
R. Locoe
中科院分区：
文献类型：
--
作者：
R. Locoe
仅提供摘要形式。当在辐射环境中使用微电子组件时，例如空间组件、核反应堆中使用的组件和用于高能物理实验的组件所经历的辐射环境，必须减轻特定的退化机制，以确保在部件的使用寿命内保持适当的组件性能。在过去的三十年里，制造辐射硬化部件的首选方法是使用具有专业工艺的精品专用铸造厂。该方法通常被称为过程硬化。然而，由于对抗辐射元件的需求量很小，以及沿着摩尔的成本呈指数级增长，这些专用代工厂的数量急剧减少，它们仍然落后于最先进的CMOS三代以上。最近，一种新的方法，在商业CMOS代工厂制造抗辐射元件已经开发出来。在这种方法中，使用非标准的晶体管拓扑结构，增加保护环和新的电路技术的应用程序的组件的辐射硬度设计。该专题介绍首先介绍了空间和地面辐射环境，然后讨论了不同辐射源对CMOS技术的影响。这包括讨论总电离剂量、单粒子翻转、单粒子闭锁和单粒子瞬态辐射效应。讨论了具体的非标准晶体管拓扑结构和保护带的应用，以减轻总剂量效应。还介绍了减轻单粒子效应的电路方法。这些设计方法的应用不会没有面积和性能损失，这是量化的一部分，本演示文稿。还讨论了与设计硬度方法应用相关的独特可靠性问题。最后，讨论了减轻地球辐射影响的问题。
Summary form only given. When using microelectronic components in a radiation environment, such as those experienced by components in space, components used in nuclear reactors and components used for high-energy physics experiments, specific degradation mechanisms must be mitigated to assure proper component performance over the lifetime of the part. Over the last thirty years, the preferred method for fabricating radiation-hardened parts has been by using boutique, dedicated foundries with specialized processes. The approach is often referred to as hardening-by-process. However, due to the small demand for radiation-hardened components and the exponentially increasing costs of advancing along Moore's, the number of these dedicated foundries has decreased dramatically and they remain more than three generations behind state-of-the-art CMOS. Recently, a novel approach for fabricating radiation-hardened components at commercial CMOS foundries has been developed. In this approach, radiation hardness is designed into the component using non-standard transistor topologies, the addition of guard rings and the application of novel circuit techniques. This presentation began with a description of the space and terrestrial radiation environments, followed by a discussion on the effects of different radiation sources on CMOS technologies. This included a discussion on total-ionizing dose, single-event upsets, single-event latchup and single-event transient radiation effects. Specific non-standard transistor topologies and the application of guard bands to mitigate total dose effects were discussed. Circuit approaches to mitigating single-event effects were also presented. The application of these design approaches does not come without area and performance penalties, which were quantified as part of this presentation. Unique reliability issues associated with the application of hardness-by-design methodologies were also discussed. Finally, a discussion on mitigating terrestrial radiation effects was presented.