Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation
Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation
复制标题
使用混合功耗估计加速片上系统功耗分析
DOI：
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发表时间：
2007
期刊：
影响因子：
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通讯作者：
A. Raghunathan
中科院分区：
文献类型：
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作者：
M. Ghodrat;K. Lahiri;A. Raghunathan
快速、准确的功耗分析是设计高能效片上系统 (SoC) 的关键要求。当前的系统级功耗分析工具无法在可接受的时间内生成实际工作负载下的功耗估计，即使对于中等复杂的 SoC 也是如此。我们的工作通过借鉴仿真来解决这个问题，仿真是一种广泛使用的加速功能验证的技术。不幸的是，由于仿真能力的限制，以及在设计过程的早期缺乏一些 SoC 组件的仿真就绪、可综合的模型，对大多数系统来说，对完整 SoC 功耗分析所需的所有功能进行硬件仿真可能是不可行的。本文介绍了混合功耗估计，这是一种通过在 FPGA 平台（甚至是低成本、现成的 FGPA 板）上模拟 SoC 组件子集的功能和功耗模型来加速 SoC 功耗分析的方法。我们描述了该框架的硬件和软件组件，并提出了克服主板通信带宽有限所带来的挑战的技术。我们使用 Xilinx Virtex-II Pro 仿真平台和 HDL 模拟器的软件扩展实现了混合功耗估计框架，以对视频解码器 SoC 进行功耗分析。结果表明，与基于仿真的功率估计相比，分析效率提高了 65-332 倍，且精度没有损失。此外，我们还表明，与纯功能仿真相比，混合功耗估计对 FPGA 资源需求的增加是适度的。
Fast and accurate power analysis is a critical requirement for designing power-efficient system-on-chips (SoCs). Current system-level power analysis tools are incapable of generating power estimates under real-life workloads within an acceptable amount of time, even for moderately complex SoCs. Our work addresses this problem by borrowing on emulation, which is a widely used technique to accelerate functional verification. Unfortunately, hardware emulation of all the necessary functions for full SoC power analysis is likely to be infeasible for most systems, due to constraints on emulation capacity, and the lack of emulation-ready, synthesizable models for some SoC components early in the design process. This paper describes hybrid power estimation, an approach to accelerating SoC power analysis by emulating the functional and power models of a subset of SoC components on an FPGA platform (even a low-cost, off-the-shelf FGPA board). We describe the hardware and software components of the framework, and propose techniques to overcome the challenges posed by limited host-board communication bandwidth. We have implemented a hybrid power estimation framework using a Xilinx Virtex-II Pro emulation platform and software extensions to an HDL simulator, to conduct power analysis of a video decoder SoC. The results indicate 65-332X gains in analysis efficiency over simulation-based power estimation, with no loss in accuracy. Further, we show that the increase in FPGA resource requirements for hybrid power estimation over pure functional emulation are modest.