The selective read-out processor for the CMS electromagnetic calorimeter
The selective read-out processor for the CMS electromagnetic calorimeter
复制标题
CMS电磁热量计的选择性读出处理器
DOI：
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复制
发表时间：
2004
影响因子：
1.8
通讯作者：
J. Varela
中科院分区：
文献类型：
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作者：
Nuno Almeida;P. Busson;J. Faure;O. Gachelin;P. Gras;I. Mandjavidze;M. Mur;J. Varela
本文介绍了为大型强子对撞机 (CERN) 紧凑型介子螺线管 (CMS) 实验的电磁量热计 (ECAL) 提出的选择性读出处理器 (SRP)。目的是将原始 ECAL 数据减少到 CMS 数据采集 (DAQ) 系统可接受的水平。对于每个正 1 级触发，SRP 由触发原语生成电子设备引导，以识别能量沉积满足某些可编程标准的 ECAL 区域。然后，它指示 ECAL 读出电子设备将预定义的零抑制水平应用于晶体数据，具体取决于晶体是否落在这些区域内。 SRP 面临的主要挑战是约 200 个高速 (1.6 Gbit/s) I/O 通道、高达 100 kHz 1 级触发率的异步操作、5-/spl mu/s 实时延迟要求以及在选择算法选择时保持灵活性的需要。 SRP 采用的架构基于现代并行光学可插拔模块和具有嵌入式处理器和多千兆位收发器的高密度现场可编程门阵列 (FPGA) 器件。提出了验证所提出的解决方案的实施研究。使用 CMS 检测器模拟软件研究了设想的选择算法的性能。光通信信道的鲁棒性是通过直接测量和计算来估计的。通过在具有 Xilinx Virtex2Pro FPGA 器件的开发板上运行代表性 SRP 固件，验证了在分配的时序预算内执行数据缩减操作的可行性。
This paper describes the selective read-out processor (SRP) proposed for the electromagnetic calorimeter (ECAL) of the Compact Muon Solenoid (CMS) experiment at LHC (CERN). The aim is to reduce raw ECAL data to a level acceptable by the CMS data acquisition (DAQ) system. For each positive level 1 trigger, the SRP is guided by trigger primitive generation electronics to identify ECAL regions with energy deposition satisfying certain programmable criteria. It then directs the ECAL read-out electronics to apply predefined zero suppression levels to the crystal data, depending whether the crystals fall within these regions or not. The main challenges for the SRP are some 200 high speed (1.6 Gbit/s) I/O channels, asynchronous operation at up to 100 kHz level 1 trigger rate, a 5-/spl mu/s real-time latency requirement and a need to retain flexibility in choice of selection algorithms. The architecture adopted for the SRP is based on modern parallel optic pluggable modules and high density field programmable gate array (FPGA) devices with embedded processors and multigigabit transceivers. Implementation studies to validate proposed solutions are presented. The performance of envisaged selection algorithms is investigated with the CMS detector simulation software. The robustness of optical communication channels is estimated via direct measurements and calculations. The feasibility to perform data reduction operations within the allocated timing budget is verified by running a representative SRP firmware on a development board with a Xilinx Virtex2Pro FPGA device.