A Neuron-MOS-Based VLSI Implementation of Pulse-Coupled Neural Networks for Image Feature Generation
A Neuron-MOS-Based VLSI Implementation of Pulse-Coupled Neural Networks for Image Feature Generation
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DOI：
10.1109/tcsi.2009.2028751
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发表时间：
2010-06-01
影响因子：
5.1
通讯作者：
Shibata, Tadashi
中科院分区：
文献类型：
--
作者：
Chen, Jun;Shibata, Tadashi
使用 Neuron-MOS (vMOS) 技术开发了一种用于在超大规模集成 (VLSI) 硬件中实现脉冲耦合神经网络 (PCNN) 的模拟电路。 PCNN 是受生物学启发的模型，具有强大的图像特征生成能力。借助 vMOS 技术，PCNN 的核心要素——多个输入信号的加权和，只需通过 vMOS 模块中的电容耦合效应即可实现。通过采用vMOS块中的开关浮栅作为临时模拟存储器，简单地实现了图像数据的存储。此外，对于模拟 PCNN 神经元动力学至关重要的衰减生成功能也通过利用其中的输入端电容器合并到 vMOS 模块中。通过这些技术，该电路以紧凑的结构实现了 PCNN 的纯电压模式实现。该电路继承了PCNN的优点，对不同模式具有良好的区分性，并对相同模式的旋转和平移具有鲁棒性，类似于人类图像感知。该电路的性能已通过对采用 0.35μm 双多晶硅 CMOS 技术制造的概念验证芯片的测量进行了验证。
An analog circuit for implementing pulse-coupled neural networks (PCNNs) in very-large-scale integration (VLSI) hardware has been developed using the Neuron-MOS (vMOS) technology. PCNNs are biologically inspired models having powerful ability for image feature generation. With the vMOS technology, weighted sum of multiple input signals, which is an essential of PCNNs, is implemented simply by the capacitive coupling effect in a vMOS block. By employing the switched floating gates in the vMOS blocks as temporary analog memories, the storage of image data is simply realized. Moreover, the function of decay generation, which is crucial for emulating PCNNs neuronal dynamics, is also merged into a vMOS block by utilizing the input-terminal capacitors in it. With such techniques, the circuit achieves a purely voltage-mode implementation of PCNNs in a compact structure. Inheriting the merits of PCNNs, the circuit has good discriminability against different patterns as well as robustness against rotation and translation of identical patterns, which is analogous to human image perception. The performance of the circuit has been verified by the measurements of a proof-of-concept chip fabricated in a 0.35-mu m double-polysilicon CMOS technology.