Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement
复制标题
DOI：
10.1145/1391469.1391610
复制
发表时间：
2008-06
期刊：
影响因子：
--
通讯作者：
Xiangyu Dong;Xiaoxia Wu;Guangyu Sun;Yuan Xie;Hai Helen Li;Yiran Chen
中科院分区：
文献类型：
--
作者：
Xiangyu Dong;Xiaoxia Wu;Guangyu Sun;Yuan Xie;Hai Helen Li;Yiran Chen
磁性随机存取存储器（MRAM）由于具有许多吸引人的特性而被认为是一种很有前途的存储技术。由于MRAM与CMOS逻辑的混合磁性-CMOS制造工艺，将MRAM与CMOS逻辑集成可能会招致额外的制造成本。使用3D集成在CMOS逻辑之上堆叠MRAM是最小化此成本开销的一种方式。在本文中，我们讨论了MRAM的电路设计问题，并提出了MRAM的高速缓存模型。基于该模型，我们比较了MRAM与SRAM和DRAM的面积，性能和能源。最后，我们进行架构评估与MRAM的三维微处理器堆叠。实验结果表明，MRAM堆叠提供了有竞争力的IPC性能与大幅度降低功耗相比，SRAM和DRAM同行。
Magnetic random access memory (MRAM) has been considered as a promising memory technology due to many attractive properties. Integrating MRAM with CMOS logic may incur extra manufacture cost, due to its hybrid magnetic-CMOS fabrication process. Stacking MRAM on top of CMOS logics using 3D integration is a way to minimize this cost overhead. In this paper, we discuss the circuit design issues for MRAM, and present the MRAM cache model. Based on the model, we compare MRAM against SRAM and DRAM in terms of area, performance, and energy. Finally we conduct architectural evaluation for 3D microprocessor stacking with MRAM. The experimental results show that MRAM stacking offers competitive IPC performance with a large reduction in power consumption compared to SRAM and DRAM counterparts.