Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect
Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect
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DOI：
10.1109/jssc.2005.845560
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发表时间：
2005-04
影响因子：
5.4
通讯作者：
N. Miura;D. Mizoguchi;T. Sakurai;T. Kuroda
中科院分区：
文献类型：
--
作者：
N. Miura;D. Mizoguchi;T. Sakurai;T. Kuroda
利用层叠芯片之间的电感耦合，设计了一种层叠芯片无线总线。本文讨论了电感布局优化和收发器电路设计。电感耦合分析了一个简单的等效电路模型，其参数提取的磁场模型的基础上的毕奥萨伐尔定律。在给定通信距离、发射功率、数据速率和SNR预算的情况下，电感器布局尺寸最小化。两个接收器电路，信号敏感，但噪声免疫，是专为感应不归零（NRZ）信号，没有信号被发送时，数据保持不变。测试芯片采用0.35-/spl μ/m CMOS工艺制作。验证了模型的准确性。误码率进行了研究，为各种电感布局和通信距离。最大数据速率为1.25 Gb/s/channel。在3.3 V时，发射器的功耗为43 mW，接收器的功耗为2.6 mW。如果在90 nm器件中芯片厚度降至30 /spl mu/m，则功耗为1 mW/通道或带宽为1 Tb/s/mm/sup 2/。
A wireless bus for stacked chips was developed by utilizing inductive coupling among them. This paper discusses inductor layout optimization and transceiver circuit design. The inductive coupling is analyzed by a simple equivalent circuit model, parameters of which are extracted by a magnetic field model based on the Biot-Savart law. Given communication distance, transmit power, data rate, and SNR budget, inductor layout size is minimized. Two receiver circuits, signal sensitive and yet noise immune, are designed for inductive nonreturn-to-zero (NRZ) signaling where no signal is transmitted when data remains the same. A test chip was fabricated in 0.35-/spl mu/m CMOS technology. Accuracy of the models is verified. Bit-error rate is investigated for various inductor layouts and communication distance. The maximum data rate is 1.25 Gb/s/channel. Power dissipation is 43 mW in the transmitter and 2.6 mW in the receiver at 3.3 V. If chip thickness is reduced to 30 /spl mu/m in 90-nm device generation, power dissipation will be 1 mW/channel or bandwidth will be 1 Tb/s/mm/sup 2/.