Maintaining packet order in two-stage switches
Maintaining packet order in two-stage switches
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DOI：
10.1109/infcom.2002.1019351
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发表时间：
2002-11
期刊：
影响因子：
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通讯作者：
I. Keslassy;N. McKeown
中科院分区：
文献类型：
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作者：
I. Keslassy;N. McKeown
高性能分组交换机经常使用集中式调度器（也称为仲裁器）来确定非阻塞交叉条的配置。由于调度程序决策的频率和复杂性，它经常限制系统的可伸缩性。c - s。Chang等人（2001）引入了一个有趣的两阶段开关，其中每一阶段使用一个平凡的确定性配置序列。该交换机在高速下易于实现，并已被证明可以为广泛的流量提供100%的吞吐量。此外，两级交换的平均延迟与理想输出排队交换的平均延迟之间存在一个界限。然而，在其最简单的形式中，交换机错误排序数据包的数量是任意的。在本文中，基于两级交换机，我们提出了一种称为全帧优先（FFF）的算法，该算法可以防止错误排序，同时保持基本两级交换机的性能优势（在吞吐量和延迟方面）。FFF需要一些额外的成本，我们在本文中对其进行了评估。
High performance packet switches frequently use a centralized scheduler (also known as an arbiter) to determine the configuration of a non-blocking crossbar. The scheduler often limits the scalability of the system because of the frequency and complexity of its decisions. A paper by C.-S. Chang et al. (2001) introduced an interesting two-stage switch, in which each stage uses a trivial deterministic sequence of configurations. The switch is simple to implement at high speed and has been proved to provide 100% throughput for a broad class of traffic. Furthermore, there is a bound between the average delay of the two-stage switch and that of an ideal output-queued switch. However, in its simplest form, the switch mis-sequences packets by an arbitrary amount. In this paper, building on the two-stage switch, we present an algorithm called full frames first (FFF), that prevents mis-sequencing while maintaining the performance benefits (in terms of throughput and delay) of the basic two-stage switch. FFF comes at some additional cost, which we evaluate in this paper.