17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology
17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology
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17.1 采用 14nm FinFET CMOS 技术的 0.6V 1.5GHz 84Mb SRAM 设计
DOI：
10.1109/isscc.2015.7063050
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发表时间：
2015
期刊：
影响因子：
--
通讯作者：
Kevin Zhang
中科院分区：
文献类型：
--
作者：
E. Karl;Z. Guo;James W. Conary;Jeffrey L. Miller;Yong;Satyanand Nalam;Daeyeon Kim;J. Keane;U. Bhattacharya;Kevin Zhang
电池供电的移动和可穿戴设备的增长增加了低功耗操作的重要性和片上系统(SoC)设计中的成本。电源电压调节是SoC设计中降低有功功率的主要方法，包括在存储器集成度不断提高的情况下对片上存储器进行电压调节。SRAM可以限制设计的最小工作电压(VMIN)，这通常会导致为片上存储器引入单独的电压源。额外的电源增加了平台成本，在更高的电压下操作内存会导致功耗增加。与现有的体平面器件技术相比，在22 nm技术节点引入的触发器器件提供了卓越的短沟道效应和亚阈值斜率，从而能够在固定的漏电约束下降低阈值电压。更低的晶体管Vth、随机器件变异性的改进以及克服器件尺寸量化的辅助电路使SRAM VMIN降低了150 mV[1]。在14 nm技术节点，对于采用最小尺寸晶体管的紧凑型6T SRAM位单元来说，FinFET器件尺寸量化仍然是一个挑战。为了在低电压下提供高密度、低功率的存储器操作，需要在存储器辅助电路的技术和设计之间仔细地协同优化。本文提出了一种采用第二代FinFET晶体管的14 nm逻辑技术的宽电压范围的84Mb SRAM阵列设计。
The growth of battery-powered mobile and wearable devices has increased the importance of low-power operation and cost in system-on-a-chip (SoC) design. Supply-voltage scaling is the predominant approach to active power reduction for SoC design, including voltage scaling for on-die memory given increasing levels of memory integration. SRAM can limit the minimum operating voltage (VMIN) of a design, often leading to the introduction of separate voltage supplies for on-die memory. Additional supplies increase platform cost, and operating memory at higher voltage leads to increased power consumption. The introduction of trigate devices at the 22nm technology node delivered superior short channel effects and subthreshold slope relative to existing bulk planar device technology enabling reduction in threshold voltage within a fixed leakage constraint. Lower transistor Vth, improvements to random device variability, and assist circuits to overcome device-size quantization enabled a >150mV reduction in SRAM VMIN [1]. At the 14nm technology node, FinFET device-size quantization remains a challenge for compact 6T SRAM bitcells with minimum-size transistors. Careful co-optimization between technology and design of memory-assist circuits is required in order to deliver dense, low-power memory operation at low voltages. In this paper, we present an 84Mb SRAM array design with wide-voltage-range operation in a 14nm logic technology featuring 2nd-generation FinFET transistors.