CAIRO
CAIRO
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DOI：
10.1145/3155287
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发表时间：
2017-12
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通讯作者：
Ramyad Hadidi;Lifeng Nai;Hyojong Kim;Hyesoon Kim
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文献类型：
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作者：
Ramyad Hadidi;Lifeng Nai;Hyojong Kim;Hyesoon Kim
三维（3D）堆叠技术和内存墙问题再次普及了内存中处理（PIM）概念，它通过将计算卸载到内存中的功能单元来提供带宽和能源节约的好处。一些内存供应商也开始将计算逻辑集成到内存中，比如混合内存立方体（Hybrid memory Cube， HMC），其最新版本支持最多18条内存原子指令。尽管行业原型激发了对PIM有效方法和架构的研究，但研究人员还没有提出一种系统的方法来确定教学级PIM卸载的好处。因此，编译器无法支持识别卸载候选项和利用指令级PIM卸载。在本文中，我们分析了用于图计算应用程序的hmc -原子指令上下文中的指令级PIM卸载的优点，并提出了CAIRO，这是一种编译器辅助技术和决策模型，可以在不给程序员带来任何负担的情况下实现PIM的指令级卸载。为了开发CAIRO，我们分析了指令卸载如何在CPU和GPU工作负载中实现性能提升。我们的研究表明，带宽节省、缓存未命中数与总缓存访问数的比率以及主机原子指令的开销是选择卸载候选对象的关键因素。基于我们的分析模型，我们描述了有利和不利的卸载候选者的特性。我们用27个多线程CPU和36个GPU基准来评估CAIRO。在我们的评估中，CAIRO不仅通过利用hmc原子指令将一组有利于pim的工作负载的加速提高了一倍，而且还防止了因其他工作负载的错误卸载决策而导致的减速。
Three-dimensional (3D)-stacking technology and the memory-wall problem have popularized processing-in-memory (PIM) concepts again, which offers the benefits of bandwidth and energy savings by offloading computations to functional units inside the memory. Several memory vendors have also started to integrate computation logics into the memory, such as Hybrid Memory Cube (HMC), the latest version of which supports up to 18 in-memory atomic instructions. Although industry prototypes have motivated studies for investigating efficient methods and architectures for PIM, researchers have not proposed a systematic way for identifying the benefits of instruction-level PIM offloading. As a result, compiler support for recognizing offloading candidates and utilizing instruction-level PIM offloading is unavailable. In this article, we analyze the advantages of instruction-level PIM offloading in the context of HMC-atomic instructions for graph-computing applications and propose CAIRO, a compiler-assisted technique and decision model for enabling instruction-level offloading of PIM without any burden on programmers. To develop CAIRO, we analyzed how instruction offloading enables performance gain in both CPU and GPU workloads. Our studies show that performance gain from bandwidth savings, the ratio of number of cache misses to total cache accesses, and the overhead of host atomic instructions are the key factors in selecting an offloading candidate. Based on our analytical models, we characterize the properties of beneficial and nonbeneficial candidates for offloading. We evaluate CAIRO with 27 multithreaded CPU and 36 GPU benchmarks. In our evaluation, CAIRO not only doubles the speedup for a set of PIM-beneficial workloads by exploiting HMC-atomic instructions but also prevents slowdown caused by incorrect offloading decisions for other workloads.