5.4 Frequency-locked-loop ring oscillator with 3ns peak-to-peak accumulated jitter in 1ms time window for high-resolution frequency counting
5.4 Frequency-locked-loop ring oscillator with 3ns peak-to-peak accumulated jitter in 1ms time window for high-resolution frequency counting
复制标题
DOI：
10.1109/isscc.2017.7870276
复制
发表时间：
2017-02
期刊：
影响因子：
--
通讯作者：
Karthik Pappu;G. Reitsma;S. Bapat
中科院分区：
文献类型：
--
作者：
Karthik Pappu;G. Reitsma;S. Bapat
Many sensing applications require a high-resolution frequency measurement. These applications include measurement of pressure, acceleration and eddy-current sensing. In these applications the sensor is part of an oscillator circuit where the physical quantity being measured is represented by a frequency. In most of these applications the supply current is dictated by the SNR requirements, therefore in order to save power, power cycling is used with a minimum conversion time. For an accurate frequency measurement this conversion time is limited by the time resolution and the accumulated jitter of the reference clock [1]. In this paper a ring oscillator with less than 3ns peak-to-peak accumulated jitter over a 1ms time window is presented. A high time resolution of 770ps is obtained by reading the state of the individual inverters of the ring oscillator. The accumulated jitter is 20 times smaller than the state of the art on-chip oscillators [2–4] and enables us to detect very small changes in physical quantities like distance, pressure, mass etc.
