A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow

A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow
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使用传统 EDA 工具实现 Pulsar QDI 设计流程的前端

DOI:
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发表时间:
2020
期刊:
2020 26th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
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通讯作者:
Ney Laert Vilar Calazans
Ney Laert Vilar Calazans
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文献类型:
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作者:
M. Sartori;Matheus T. Moreira;Ney Laert Vilar Calazans

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异步准延迟不敏感电路以其对变化的鲁棒性而闻名,但由于缺乏足够的设计方法以及缺乏设计和验证工具,它们的广泛使用一直是牺牲品。最近提出的脉冲星流使准延迟不敏感电路的设计和优化,使用传统的EDA工具,增强了足够的库,方法和模型。Pulsar使设计人员能够在时间预算松弛时自然地以性能换取功率或面积。然而,Pulsar缺乏自动双轨扩展方法来支持其操作,需要设计人员手动开发时序模型作为异步周期时间约束计算的输入。本文提出并描述了脉冲星前端的特点。Pulsar-F,新的流量版本可用作异步QDI电路的按钮设计工具。Pulsar-F为Pulsar增加了以下功能:(i)基于RTL的设计捕获方法;(ii)使用商业EDA工具的启发式、时序驱动的单轨预综合过程;(iii)具有细粒度确认网络生成的双轨扩展技术;(iv)一种工具,该工具自动计算半缓冲通道网络(HBCN)基于图形的时序模型,用于预实验表明,Pulsar-F改进了Pulsar,进一步帮助异步设计人员权衡功耗、面积和性能。
Asynchronous quasi-delay-insensitive circuits are known for their robustness against variations, but their widespread use has been prey to the absence of adequate design methods and lack of design and verification tools. The recently proposed Pulsar flow enables the design and optimisation of quasi-delay-insensitive circuits using conventional EDA tools, enhanced by adequate libraries, methods and models. Pulsar enables designers to naturally trade performance for power or area, whenever there is slack in timing budgets. However, Pulsar lacked an automated dual-rail expansion method to support its operation, requiring that designers manually develop a timing model as input to the computation of asynchronous cycle time constraints. This paper proposes and describes the features of a frontend for Pulsar. Pulsar-F, the new flow version can be used as a push-button design tool for asynchronous QDI circuits. Pulsar-F adds the following features to Pulsar: (i) an RTL-based design capture method; (ii) a heuristic, timing-driven singlerail pre-synthesis process using commercial EDA tools; (iii) a dual-rail expansion technique with fine-grain acknowledgement network generation; (iv) a tool that automates the computation of the Hal-Buffer Channel Network (HBCN) graph-based timing model for pre-synthesised circuits and derives a set of timing constraints for it. Experiments show that Pulsar-F improves Pulsar to further aid asynchronous designers to trade off power, area and performance.