Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application
Junctionless Poly-Si Nanowire Transistors With Low-Temperature Trimming Process for Monolithic 3-D IC Application
复制标题
适用于单片 3D IC 应用的采用低温微调工艺的无结多晶硅纳米线晶体管
DOI：
10.1109/ted.2016.2615805
复制
发表时间：
2016
影响因子：
3.1
通讯作者：
T. Chao
中科院分区：
文献类型：
--
作者：
Jer;P. Kuo;K. Lin;C. Chin;T. Chao
本文采用低温微调工艺，成功地制备了栅极环绕型、源漏升高的无结(JL)超薄多晶硅(多晶硅)纳米线(NW)晶体管。采用140°C加热的磷酸(HPA)对沟道尺寸进行微调，具有接近粗糙度的无退化刻蚀和良好的微调均匀度。随着HPA浸泡时间的增加，沟道尺寸变薄变窄，静电完整性增强。因此，可以实现陡峭的亚阈值摆幅~75 mV/ten，低漏感势垒降低~33 mV/V，高通断电流比(ion/IOff)~7×106。低温JL多晶硅NW晶体管的这些优越特性是未来低热预算单片3-D集成电路和面板上系统应用的潜在候选者。
In this paper, the junctionless (JL) ultrathin polycrystalline-Si (poly-Si) nanowire (NW) transistors with gate-all-around configuration and raised source/drain were successfully fabricated by a low-temperature trimming process. The 140 °C-heated phosphoric acid (HPA) was adopted for trimming the channel dimension, which exhibits a near roughness degradation-free etching and excellent trimming uniformity. As the HPA immersing time increased, the channel dimension was thinned and narrowed, resulting in the greater electrostatic integrity. Therefore, the steep subthreshold swing ~75 mV/decade, low drain-induced barrier lowering ~33 mV/V, and high on/off currents ratio (ION/IOFF) ~ 7 x 106 can be achieved. These superior characteristics of low-temperature JL poly-Si NW transistors are promising candidates for the low thermal budget monolithic 3-D ICs and the system on panel applications in the future.