An Integrated Full-Duplex/FDD Duplexer and Receiver Achieving 100MHz Bandwidth 58dB/48dB Self-Interference Suppression Using Hybrid-Analog-Digital Autonomous Adaptation Loops
An Integrated Full-Duplex/FDD Duplexer and Receiver Achieving 100MHz Bandwidth 58dB/48dB Self-Interference Suppression Using Hybrid-Analog-Digital Autonomous Adaptation Loops
复制标题
使用混合-模拟-数字自主适应环路实现 100MHz 带宽 58dB/48dB 自干扰抑制的集成全双工/FDD 双工器和接收器
DOI:
--
复制
发表时间:
2020
期刊:
影响因子:
--
通讯作者:
Jin Zhou
中科院分区:
文献类型:
--
作者:
Yuhe Cao;Xuanzhen Cao;Hyungjoo Seo;Jin Zhou
This paper presents a 1.5-to-2 GHz CMOS electrical-balance duplexer and receiver supporting both frequency-division duplexing (FDD) and in-band full-duplex (IBFD) operations. The proposed multi-tap and multi-stage RF and analog self-interference cancellation adapts itself autonomously to a time-varying channel in real time using a new on-chip hybrid-analog-digital adaptation loop. A $G_{m}-C$-based reconfigurable frequency shift is utilized to support FDD operation. In measurement, 58dB and 48dB RF/analog self-interference suppression are achieved across a 100MHz bandwidth in the IBFD and the FDD mode, respectively. Using the proposed embedded adaptation loops, <50µs adaptation is achieved without any high-speed ADC or DSP.