Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology
Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology
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采用新型多激光尖峰退火方案的结轮廓工程，适用于 45 nm 节点高性能和低泄漏 CMOS 技术
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发表时间：
2007
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通讯作者：
T. Sugii
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作者：
T. Yamamoto;T. Kubo;T. Sukegawa;E. Takii;Y. Shimamune;N. Tamura;T. Sakoda;M. Nakamura;H. Ohta;T. Miyashita;H. Kurata;S. Satoh;M. Kase;T. Sugii
我们开发了一种新的结型工程，它使用了一种最新开发的多激光尖峰退火方案，并将其应用于45 nm结点高性能和低泄漏的CMOS工艺。这种新的结型工程对于在PMOS区域嵌入SiGe的CMOS器件的性能改善是有效的。降低了源漏寄生电阻和结漏电流，从而提高了33 nm CMOS器件的离子强度(PMOS/NMOS的Ioff=9[nA/um]时为8.2%/12.8%)。我们还证明了氟共注入在降低PMOS源漏扩展(SDE)电阻方面起到了很大的作用。
We developed novel junction profile engineering that uses a newly developed multiple laser spike annealing scheme and applied it to 45-nm node high performance and low leakage CMOS technology. This novel junction profile engineering is effective for the performance improvement of CMOS devices with embedded SiGe in the PMOS regions. Reduction of the source-drain parasitic resistance and the junction leakage current were achieved, thus improving the Ion of 33-nm CMOS devices (8.2% / 12.8% with an Ioff = 9 [nA/mum] for PMOS / NMOS). We also demonstrate that the fluorine co-implant plays a large role in reducing the PMOS source-drain extension (SDE) resistance.