Technology for integrated circuit micropackages for neural interfaces, based on gold-silicon wafer bonding
Technology for integrated circuit micropackages for neural interfaces, based on gold-silicon wafer bonding
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DOI：
10.1088/0960-1317/23/7/075021
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发表时间：
2013-07-01
影响因子：
2.3
通讯作者：
Donaldson, N.
中科院分区：
文献类型：
--
作者：
Saeidi, N.;Schuettler, M.;Donaldson, N.
有源神经接口器件的发展需要一种非常紧凑的方法来保护集成电路（IC）。本文详细介绍了一种微封装的成型方法。在使用Au-Si共晶的晶片键合工艺中，芯片的有源区被密封在帽晶片的充气腔中。我们描述了简单的添加到IC的设计，后处理的活性晶圆和所需的功能的帽晶圆。在互补金属氧化物半导体IC公差范围内的压力和温度水平下进行的键合强度足以满足MIL STD 883 G方法2019.8（剪切力测试）。我们的结果表明，建议使用FTIR的晶圆级总泄漏测试的方法。这种微封装方法不需要特殊的制造工艺，并且基于使用IC兼容或传统的制造步骤。
Progress in the development of active neural interface devices requires a very compact method for protecting integrated circuits (ICs). In this paper, a method of forming micropackages is described in detail. The active areas of the chips are sealed in gas-filled cavities of the cap wafer in a wafer-bonding process using Au-Si eutectic. We describe the simple additions to the design of the IC, the post-processing of the active wafer and the required features of the cap wafer. The bonds, which were made at pressure and temperature levels within the range of the tolerance of complementary metal-oxide-semiconductor ICs, are strong enough to meet MIL STD 883G, Method 2019.8 (shear force test). We show results that suggest a method for wafer-scale gross leak testing using FTIR. This micropackaging method requires no special fabrication process and is based on using IC compatible or conventional fabrication steps.