1.5–3.3 GHz, 0.0077 mm2, 7 mW All-Digital Delay-Locked Loop With Dead-Zone Free Phase Detector in $0.13~\mu \text{m}$ CMOS
1.5–3.3 GHz, 0.0077 mm2, 7 mW All-Digital Delay-Locked Loop With Dead-Zone Free Phase Detector in $0.13~\mu \text{m}$ CMOS
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1.5–3.3 GHz、0.0077 mm2、7 mW 全数字延迟锁定环，带无死区相位检测器，采用 $0.13~mu ext{m}$ CMOS
DOI：
10.1109/tcsi.2017.2715899
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
R. Negra
中科院分区：
文献类型：
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作者：
Erkan Bayram;A. Aref;M. Saeed;R. Negra
提出了一种采用UMC 130纳米CMOS技术设计的1.5-3.3 GHz、7 mW全数字锁相环（ADDLL）。该算法采用改进的逐次逼近寄存器来控制基于nand的粗延迟线，从而实现更宽的工作频率范围和较小的固有延迟。采用基于xor的上下计数器和无死区鉴相器控制基于逆变器的细延迟线，克服了传统鉴相器存在的死区问题。对鉴相器中的d型触发器进行修改，检测输入输出时钟之间的亚ps级延迟差，从而实现优于1ps的延迟分辨率。粗锁和细锁相结合，在剩余相位差和输出抖动方面表现优异。整体设计面积为0.0077 mm2。实验结果表明，该系统在3.3 GHz时的峰值抖动和均方根抖动分别为12和1.629 ps，而输入抖动分别为2.6 ps和612 fs rms。
A 1.5–3.3 GHz, 7 mW, all-digital delay-locked loop (ADDLL) designed in a UMC 130-nm CMOS technology is presented in this paper. The proposed ADDLL uses the modified successive approximation register to control a NAND-based coarse delay line, which enables wider operating frequency range and small intrinsic delay. The inverter-based fine delay line is controlled by an XOR-based up/down counter with dead-zone free phase detector to overcome the dead-zone problem of conventional phase detectors. The D-type flip-flops in the phase detector are modified to detect sub-ps level delay difference between the input and output clocks, so that a delay resolution of better than 1 ps is achieved in the proposed design. The combination of both coarse and fine locking processes gives outstanding performance in terms of residual phase difference and output jitter. The overall design occupies 0.0077 mm2 area. The experimental results show that the peak-to-peak and root mean square jitters are 12 and 1.629 ps at 3.3 GHz, respectively, while the input jitter is 2.6 ps peak-to-peak and 612 fs rms.