Design sensitivities to variability: extrapolations and assessments in nanometer VLSI
Design sensitivities to variability: extrapolations and assessments in nanometer VLSI
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设计对可变性的敏感性：纳米 VLSI 的外推和评估
DOI：
10.1109/asic.2002.1158094
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发表时间：
2002
期刊：
影响因子：
--
通讯作者：
Jie Yang
中科院分区：
文献类型：
--
作者：
Yu Cao;Puneet Gupta;A. Kahng;D. Sylvester;Jie Yang
我们提出了一个新的框架来评估（1）工艺变化对电路性能和产品价值的影响，以及（2）替代工艺改进的投资回报。我们的框架的元素包括精确的器件模型和电路仿真，沿着与蒙特-卡罗分析，估计参数收益率。我们评估的优点，考虑到这些以前未考虑的现象，工艺参数之间的相关性。我们还评估了工艺变化对相关指标的影响，如销售点的参数产量和所需的设计保护带。我们的实验结果通过接下来的两个ITRS技术节点产生了对过程变化影响的缩放的见解。
We propose a new framework for assessing (1) the impact of process variation on circuit performance and product value, and (2) the respective returns on investment for alternative process improvements. Elements of our framework include accurate device models and circuit simulation, along with Monte-Carlo analyses, to estimate parametric yields. We evaluate the merits of taking into account such previously unconsidered phenomena as correlations among process parameters. We also evaluate the impact of process variation with respect to such relevant metrics as parametric yield at selling point, and amount of required design guardbanding. Our experimental results yield insights into the scaling of process variation impacts through the next two ITRS technology nodes.