Teaching digital system design using VHDL
Teaching digital system design using VHDL
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使用 VHDL 教学数字系统设计
DOI：
10.1109/fie.1994.580478
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发表时间：
1994
期刊：
影响因子：
--
通讯作者：
C. H. Roth
中科院分区：
文献类型：
--
作者：
C. H. Roth
本文介绍了VHDL语言在数字系统设计高级课程教学中的应用。VHDL是VHSIC硬件描述语言的缩写。VHDL是一种通用语言，可用于描述和模拟各种数字系统的操作，其复杂性从几个门到许多复杂集成电路的互连。VHDL最初是为军事开发的，允许使用统一的方法来指定数字系统。VHDL已成为IEEE标准，并在美国和欧洲的工业中得到广泛应用。
This paper describes how VHDL may be used in teaching a senior course in digital systems design. The acronym VHDL stands for VHSIC Hardware Description Language. VHDL is a general-purpose language which can be used to describe and simulate the operation of a wide variety of digital systems ranging in complexity from a few gates to an interconnection of many complex integrated circuits. VHDL was originally developed for the military to allow a uniform method for specifying digital systems. VHDL has since become an IEEE standard and it is becoming widely used in industry in the United States as well as in Europe.