Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique
Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique
复制标题
使用请求屏蔽技术的低延迟片上网络路由器微架构
DOI：
--
复制
发表时间：
2015
影响因子：
4.3
通讯作者：
M. N. Marsono
中科院分区：
文献类型：
--
作者：
Alireza Monemi;C. Y. Ooi;M. N. Marsono
片上网络（NoC）作为众核片上系统（SoC）的片上通信替代方案正在迅速兴起。然而，设计具有低面积开销的高性能低延迟NoC仍然是一个挑战。在本文中，我们提出了一个两个时钟周期的延迟片上网络微架构。提出了一种有效的请求掩蔽技术，将联合收割机虚拟信道（VC）分配与交换机分配非推测地结合起来。我们提出的NoC架构的面积开销，工作频率和服务质量（QoS）方面进行了优化。我们评估我们的片上网络，针对现场可编程门阵列（FPGA）的开源低延迟片上网络设计。在几个FPGA器件上的实验结果表明，我们的NoC路由器的性能优于CNOECT的逻辑单元（LC）的利用率减少50%，而它的工作频率高100%和35%-20%相比，一个和两个时钟周期的延迟CNOECT的NoC路由器，分别。此外，所提出的NoC路由器实现了2.3倍更好的性能相比，OSCECT。
Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%-20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.