An effective congestion-driven placement framework
An effective congestion-driven placement framework
复制标题
有效的拥塞驱动的放置框架
DOI：
10.1109/tcad.2003.809662
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发表时间：
2003
期刊：
影响因子：
--
通讯作者：
André Rohe
中科院分区：
文献类型：
--
作者：
Ulrich Brenner;André Rohe
我们提出了一种快速，但可靠的方法来检测路由的关键在非常大规模的集成芯片。此外，我们展示了如何将这种拥塞估计可以纳入基于分区的布局算法。与以前的方法不同，我们不重复的放置算法的部分或应用postplacement优化，但我们使用我们的拥塞估计器的动态避免在一个单一的运行的布局算法的可布线性问题。最多1300000细胞的芯片上的计算实验。该框架减少了最关键的布线边缘的使用，平均为9.0%，布局的运行时间增加约8.7%。然而，由于较小的拥塞，布线工具的运行时间可以大大减少，因此布局和（全局）布线的总时间平均减少了47%。
We present a fast but reliable way to detect routing criticalities in very large scale integration chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a postplacement optimization, but we use our congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Computational experiments on chips with up to 1300000 cells are presented. The framework reduces the usage of the most critical routing edges by 9.0% on average, the running time increase for the placement is about 8.7%. However, due to the smaller congestion, the running time of routing tools can be decreased drastically, so the total time for placement and (global) routing is decreased by 47% on average.