Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs”
Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs”
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DOI：
10.1109/tns.2004.827944
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发表时间：
2003-12
影响因子：
1.8
通讯作者：
M. Ceschia;M. Violante;M. Sonza-Reorda;A. Paccagnella;P. Bernardi;M. Rebaudengo;D. Bortolato;M. Bellato;P. Zambolin;A. Candelori
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作者：
M. Ceschia;M. Violante;M. Sonza-Reorda;A. Paccagnella;P. Bernardi;M. Rebaudengo;D. Bortolato;M. Bellato;P. Zambolin;A. Candelori
本文介绍了使用重离子对商用现成的基于 SRAM 的现场可编程门阵列 (FPGA) 进行的辐射测试。已经进行了测试实验来识别配置存储器中的单事件扰动 (SEU) 并对其进行分类，这些扰动会引起用户实现的电路的单事件功能中断。此外，本文提出了一种基于辐射测试和基于模拟的故障注入工具相结合来评估 SEU 效果的新方法。第一个实验结果表明，FPGA 查找表 (LUT) 资源（用于实现组合逻辑）对 SEU 最敏感，而互连资源对于器件横截面最为关键，因为它们使用最多数量的配置位。对实验数据的分析强调，影响互连的最可能的错误是两个网络的短路。这一观察表明，新的故障模型应与设计容错架构的经典固定模型一起考虑，这些模型旨在在 FPGA 器件中实现。
This paper presents the radiation testing of a commercial-off-the-shelf SRAM-based field-programmable gate arrays (FPGAs) with heavy ions. Test experiments have been conducted to identify and to classify the single-event upsets (SEUs) in the configuration memory that induce single-event functional interrupt for the user-implemented circuit. Moreover the paper presents a new approach for assessing the effects of SEUs based on the combination of radiation testing and simulation-based fault injection tool. First experimental results show the FPGA look-up table (LUT) resources (used to implement combinatorial logic) are the most sensitive to SEUs, whereas interconnect resources are the most critical for the device cross section because they use the largest number of configuration bits. The analysis of experimental data underlines that the most probable error affecting interconnections is the shorting of two nets. This observation indicates that new fault models should be considered along with the classic stuck-at one model designing fault-tolerant architectures, which are intended for implementation in FPGA devices.