A 2-V CMOS cellular transceiver front-end
A 2-V CMOS cellular transceiver front-end
复制标题
2V CMOS 蜂窝收发器前端
DOI：
10.1109/4.890303
复制
发表时间：
2000
影响因子：
5.4
通讯作者：
N. Itoh
中科院分区：
文献类型：
--
作者：
M. Steyaert;J. Janssens;B. D. Muer;M. Borremans;N. Itoh
这项工作提出了一个2 V的蜂窝收发器前端在一个标准的0.25-/spl μ/m CMOS技术的设计和实施。该原型在单个芯片上集成了低中频接收机（低噪声放大器、I/Q混频器和VGA）和直接上变频发射机（I/Q混频器和前置放大器），以及完整的锁相环，包括64/79预分频器、全集成环路滤波器和带片内电感的正交压控振荡器。在不同构建块的边界上进行了设计权衡，以优化整体系统性能。所有构建模块都具有电路拓扑结构，能够在低电压下舒适地工作。因此，该IC仅需2 V电源即可工作，而接收器（RX）模式下的功耗为191 mW，发射器（TX）模式下的功耗为160 mW。要构建一个完整的1.8 GHz蜂窝通信收发器系统，只需在模拟前端添加一个天线、一个天线滤波器、一个功率放大器和一个数字基带芯片。这项工作表明，在一个标准的0.25-/SPL μ/m CMOS技术，实现I/II类DCS-1800蜂窝系统所需的模拟性能的潜力，没有调整或修剪。
This work presents the design and implementation of a 2-V cellular transceiver front-end in a standard 0.25-/spl mu/m CMOS technology. The prototype integrates a low-IF receiver (low noise amplifier, I/Q mixers, and VGAs) and a direct-upconversion transmitter (I/Q mixers and pre-amplifier) on a single die together with a complete phase-locked loop, including a 64/79 prescaler, a fully integrated loop filter, and a quadrature voltage controlled oscillator with on-chip inductors. Design trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low voltage. As a result, the IC operates from a power supply of only 2 V, while consuming 191 mW in receiver (RX) mode and 160 mW in transmitter (TX) mode. To build a complete transceiver system for 1,8-GHz cellular communication, only an antenna, an antenna filter, a power amplifier, and a digital baseband chip must be added to the analog front-end. This work shows the potential of achieving the analog performance required for the class I/II DCS-1800 cellular system in a standard 0.25-/spl mu/m CMOS technology, without tuning or trimming.