Chip Substrate Resistance Modeling Technique for Integrated Circuit Design
Chip Substrate Resistance Modeling Technique for Integrated Circuit Design
复制标题
集成电路设计的芯片衬底电阻建模技术
DOI：
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发表时间：
1984
影响因子：
2.9
通讯作者：
Wen Wang
中科院分区：
文献类型：
--
作者：
T. A. Johnson;R. Knepper;Victor Marcello;Wen Wang
随着超大规模集成电路的出现和使用统计仿真技术进行集成电路设计，芯片衬底电阻建模对成功的芯片设计变得越来越重要。本文将介绍一种可应用于FET和双极芯片设计的衬底电阻建模技术。在简要介绍了该技术背后的理论之后，我们将描述其在开发研究高速阵列芯片遇到的干扰问题所需的衬底电阻模型中的用途。将描述构建和简化基板模型所涉及的步骤。对电路模拟和噪声灵敏度的影响将随后显示。
With the advent of VLSI and the use of statistical simulation techniques to perform integrated circuit design, modeling of chip substrate resistance is becoming increasingly important to successful chip design. This paper will present a substrate resistance modeling technique which may be applied to the design of both FET and bipolar chips. After briefly presenting the theory behind the technique, we will describe its use in developing a substrate resistance model required for studying a disturb problem encountered with a high-speed array chip. The steps involved in building and simplifying the substrate model will be described. The effect on circuit simulations and noise sensitivity will then be shown.