Influence of Buffer Layer on DC and RF Performance of 4H SiC MESFET
Influence of Buffer Layer on DC and RF Performance of 4H SiC MESFET
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DOI:
10.4028/www.scientific.net/msf.457-460.1193
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发表时间:
2004-06
期刊:
影响因子:
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通讯作者:
A. Los;M. Mazzola;D. Kajfez;B. Mcdaniel;C.E. Smith;J. Kretchmer;L. Rowland;J. Casady
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文献类型:
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作者:
A. Los;M. Mazzola;D. Kajfez;B. Mcdaniel;C.E. Smith;J. Kretchmer;L. Rowland;J. Casady
DC and RF characteristics are compared for power 4H-SiC MESFETs fabricated on semi-insulating substrates, with and without a low-doped p-type buffer layer. Output admittance and gate contact thermal spectroscopy measurements are performed to analyze carrier trapping phenomena at the substrate-channel interface. Measurements indicate trapping of free carriers by vanadium acceptor at the channel-substrate interface in devices without the buffer. In the case of devices with the buffer, neither the frequency dispersion of the output or gate admittance nor the gate capacitance transient was observed. Measurements of S-parameters are performed on the MESFETs in the frequency range 0.045-5 GHz. Measurement results are used to build MESFET equivalent circuit.