Early-stage power grid analysis for uncertain working modes
Early-stage power grid analysis for uncertain working modes
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DOI：
10.1145/981066.981095
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发表时间：
2004-04
影响因子：
2.9
通讯作者：
Haifeng Qian;S. Nassif;S. Sapatnekar
中科院分区：
文献类型：
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作者：
Haifeng Qian;S. Nassif;S. Sapatnekar
高性能集成电路现在已经达到了100瓦以上的水平，电力输送和电网信号完整性已经变得至关重要。分析电力输送系统的性能需要了解组成典型分层设计的功能块所消耗的电流。然而，当前的设计是如此复杂，以至于设计者很难确定各种块的实际最坏情况切换模式将是什么，以便最大化特定位置的噪声。本文利用芯片的功耗信息，在设计的早期阶段推导出了最坏情况下的压降上限。首先建立了精确整数线性规划(ILP)方法，然后提出了一种有效的启发式算法来加快精确算法的速度。对一个43K节点的电路在70个S范围内进行了分析，发现最坏情况与ILP求解器的结果有很好的相关性。
High-performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance of the power delivery system requires knowledge of the current drawn by the functional blocks that comprise a typical hierarchical design. However, current designs are of such complexity that it is difficult for a designer to determine what a realistic worst-case switching pattern for the various blocks would be in order to maximize noise at a specific location. This paper uses information about the power dissipation of a chip to derive an upper bound on the worst-case voltage drop at an early stage of design. An exact integer linear programming (ILP) method is first developed, followed by an effective heuristic to speed up the exact method. A circuit of 43 K nodes is analyzed within 70 s, and the worst-case scenarios found correlate well with the results from an ILP solver.