Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously
Effective algorithm for integrating clock gating and power gating to reduce dynamic and active leakage power simultaneously
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DOI：
10.1109/isqed.2011.5770706
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发表时间：
2011-03
期刊：
影响因子：
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通讯作者：
Li Li-Li;K. Choi;Haiqing Nan
中科院分区：
文献类型：
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作者：
Li Li-Li;K. Choi;Haiqing Nan
时钟门控和功率门控是两种最广泛使用的技术，分别用于降低动态功耗和泄漏功率。希望这两种技术能够集成。本文采用活动驱动的优化总线特定时钟门控（OBSC）来降低动态功耗，并将OBSC生成的使能信号用作功率门控的睡眠信号。功率门控单元由所提出的前向遍历算法确定。此外，最小空闲时间概念用于确定功率门控的插入是否会获得能量减少。为了评估我们的技术，对 ISCAS'89 电路进行了实验。仿真结果证明，OBSC可降低25.07%的动态功耗，功率门控可节省45.12%的有源泄漏功率。
Clock gating and power gating are the two most widely used techniques to reduce dynamic power and leakage power respectively. It is desired that these two techniques can be integrated. In this paper, activity-driven optimized bus specific clock gating (OBSC) is applied to reduce dynamic power, and the enable signal generated by OBSC is used as the sleep signal for power gating. The power gated cells are determined by a proposed forward traversing algorithm. Moreover, minimum idle time concept is used to determine if the insertion of power gating will gain energy reduction. In order to evaluate our technique, ISCAS'89 circuits have been experimented. The simulation results prove that 25.07% dynamic power can be reduced by OBSC, and 45.12% active leakage power can be saved by power gating.