A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>m CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration
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利用脉冲的 0.18-<inline-formula> <tex-math notation="LaTeX">$mu$ </tex-math> </inline-formula>m CMOS 中的 16 位 2.0-ps 分辨率两步 TDC
DOI：
10.1109/tvlsi.2018.2867505
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发表时间：
2019
影响因子：
2.8
通讯作者：
Asada Kunihiro
中科院分区：
文献类型：
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作者：
Enomoto Ryuichi;Iizuka Tetsuya;Koga Takehisa;Nakura Toru;Asada Kunihiro
本文提出了一种时间-数字转换器（TDC），可以同时实现宽输入范围和高时间分辨率。本文提出的TDC在第二阶段采用脉冲收缩（PS）方案以获得较好的分辨率，在大范围内采用两步（TS）架构。提出的PS TDC通过利用内置的偏移脉冲和偏移脉冲宽度检测方案，防止了传统PS TDC中不希望出现的不均匀收缩率问题。采用多种技术，包括内置粗增益校准机制，所提出的TS架构克服了由于信号传播和粗级与细级之间增益不匹配而导致的非线性。仿真结果表明，采用0.18 μm标准CMOS技术实现的TDC具有2.0 ps的分辨率和16位范围，对应于~130-ns的输入时间间隔，面积为0.08 mm2。它的工作速度为3.3 MS/s， 1.8 v电源为18.0 mW，单次射击精度为1.44 ps。
This paper proposes a time-to-digital converter (TDC) that achieves wide input range and fine time resolution at the same time. The proposed TDC utilizes pulse-shrinking (PS) scheme in the second stage for a fine resolution and two-step (TS) architecture for a wide range. The proposed PS TDC prevents an undesirable nonuniform shrinking rate issue in the conventional PS TDCs by utilizing a built-in offset pulse and an offset pulsewidth detection schemes. With several techniques, including a built-in coarse gain calibration mechanism, the proposed TS architecture overcomes a nonlinearity due to the signal propagation and gain mismatch between coarse and fine stages. The simulation results of the TDC implemented in a 0.18-μm standard CMOS technology demonstrate 2.0-ps resolution and 16-bit range that corresponds to ~130-ns input time interval with 0.08-mm2area. It operates at 3.3 MS/s with 18.0 mW from 1.8-V supply and achieves 1.44-ps single-shot precision.